3-terminal tungsten CMOS-NEM relay

Abstract

Ahstract-The present work describes the design, fabrication and experimental results of a 3-terminal laterally actuated tung sten nanoelectromechanical (NEM) relay which is monolithically integrated in a 0.35 J.lm commercial standard CMOS technology. The movable structure is released by means of a simple one-step maskless wet etching. The switch shows an abrupt switching with less than 5 mY/decade and a good on-off current ratio of rv 104 although it exhibits an on-state contact resistance RON around 500 Mn. Also, the relay is cycled up to 1500 times in ambient conditions showing great endurance but variability in its contact.Nowadays we live in a digital era surrounded by plenty of electronic devices that have become a pervasive part of our daily lives, available everywhere and anytime. This fact has been possible thanks to the rapid growth in integrated circuit (lC) technology over the last decades. As we know, the main block of these electronic devices is the IC chip which is generally built using the technology so-called complementary metal oxide semiconductor (CMOS) that uses symmetric pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) to achieve complementary switching behaviour.Basically, the rapid CMOS technology advancement was achieved following simple scaling rules to reduce the dimen sions of the metal oxide semiconductor (MOS) transistors, thus achieving better performance and more integration density, reaching more functionality per chip and reduced cost per area [1]. However, in the deep-submicron regime is increasingly difficult to continue this scaling-down approach: a power crisis has emerged due to a fundamental issue inherent in the MOSFET operating principle [2, 3].The CMOS circuit power dissipation can be expressed as a sum of two power dissipation mechanisms [4]: active power dissipation PA and standby power dissipation Ps which are given bywhere in (1), K is the switching factor, C is the total capacitance and f is the operating clock frequency. In (2), IOFF is the total leakage current. VDD is the applied voltage in both terms.As CMOS is scaled to smaller dimensions and the supply voltage VDD is reduced to maintain reliability and reasonable active power dissipation, the threshold voltage VTH needs to 978-1-4799-4994-6/14/$3l.00 ©20 14 IEEE be scaled down at the same rate as VDD in order to achieve the desired circuit switching speed [4]. However, the supply voltage is not expected to be scaled down further in smaller technology nodes due to the thermal limit kBT/q [5], where kB is the Boltzmann constant, T is the temperature and q is the elementary charge. As a result, the Ps is increasing rapidly becoming the dominant factor in total power dissipation at small channel lengths. Nanoelectromechanical (NEM) relays are proposed to solve the standby power dissipation problem because they have zero leakage current and abrupt ON/OFF transition, since the device can be considered as an ideal switch. In fact, the use of mechanical switches for computing is no...

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

“…NEM-memory-based CBs show the lowest energy consumption. In addition, small chip area is feasible when NEM memory switches are integrated over a CMOS baseline chip [20]. Table II shows that the NEMmemory-based CBs exhibit the highest performance and the lowest energy consumption.…”

“…Then, States 1 and 2 are switched whenever data signal path change is needed. The proposed NEM memory switches can be easily integrated with CMOS circuits using back-end-of-line process [20].…”

Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits

“…Also, the former show faster data signal transfer and lower static power consumption than the latter due to the low-resistive metal line and zero off-state leakage current of NEM switches, respectively. Although there have been several studies on CMOS-NEM reconfigurable circuits, most of them only proposed their concepts, showed simulation results or implemented only NEM relays [2]- [7]. Although one previous research implemented CMOS-NEM hybrid circuits, it did not show reconfigurable circuit operation and stable and nonvolatile data signal paths [1].…”

“…C OMPLEMENTARY metal-oxide-semiconductor (CMOS)nano-electromechanical (NEM) reconfigurable circuits have some advantages over CMOS-only ones [1]- [7]. First, the former have smaller chip area than the latter because the routing parts using NEM switches are located over CMOS logic parts.…”

Encapsulation of NEM Memory Switches for Monolithic-Three-Dimensional (M3D) CMOS-NEM Hybrid Circuits

“…CMOS-nanoelectromechanical (CMOS-NEM) hybrid circuits have been researched intensively thanks to their unique advantages: low-power consumption, high performance, low fabrication cost and high chip density [1]- [7]. Some pioneering experimental results of CMOS-NEM hybrid circuits have been reported [2], [5].…”