32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

Doi, Yoshihiro; Shibasaki, Takayuki; Danjo, Takumi; Chaivipas, Win; Hashida, Takushi; Miyaoka, Hiroki; Hoshino, Masanori; Koyanagi, Yoichi; Yamamoto, Takuji; Tsukamoto, Sanroku; Tamura, Hirotaka

doi:10.1109/isscc.2013.6487626

Cited by 12 publications

(1 citation statement)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Current transmission rates need to be higher between large scale integration circuits (LSI). Thus, a 25.8 Gbps/lane transceiver with an 8-lane re-timer integrated circuit (IC) was developed [1,2]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Kogo

Norimatsu

Kohmu

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

A transceiver for a 25.8 Gbps/lane with a re-timer IC has been developed for information and communication equipment. Since a 1-unit interval (UI) is very narrow at 38.8 ps at 25.8 Gbps, power integrity (PI) jitter due to power supply fluctuation cannot be ignored. In this paper, we proposed a decoupling-capacitors (Decaps) placement technique to reduce power distribution network impedance (Zpdn) and a circuit design procedure regarding power supply fluctuation. The re-timer IC adopted from the proposed procedure achieved a bit error rate (BER) lower than 1 × 10 −12 on backplane transmission with an insertion loss (IL) of 40 dB.

show abstract

Section: Introductionmentioning

confidence: 99%

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Kogo

Norimatsu

Kohmu

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

Optical‐Electrical‐Optical (O‐E‐O) Switches

Mukherjee

2022

Optical Switching

View full text Add to dashboard Cite

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Hong

Chen

2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

View full text Add to dashboard Cite

A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm 2 only.

show abstract

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

Cited by 12 publications

References 6 publications

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Optical‐Electrical‐Optical (O‐E‐O) Switches

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Contact Info

Product

Resources

About

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

Cited by 12 publications

References 6 publications

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Optical‐Electrical‐Optical (O‐E‐O) Switches

A 3.12 pJ/bit, 19&#x2013;27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery

Contact Info

Product

Resources

About

A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery