3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Abstract

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

First-Principles Study of Cu Addition on Mechanical Properties of Ni3Sn4-Based Intermetallic Compounds

“…Three-dimensional electronic packaging technology can meet the high-density assembly performance requirements of today's electronic products while also providing high reliability, fast transmission speeds, low power consumption, low cost, and light weight [1][2][3]. At the same time, there can be concerns about the reliability of solder joints as they become smaller and smaller [4].…”

Simulation for Cu Atom Diffusion Leading to Fluctuations in Solder Properties and Cu6Sn5 Growth during Multiple Reflows

“…In particular, multiple reflow is an inevitable and commonly used packaging process in 3D electronic packaging technology, spawned by the trend towards the miniaturization of electronic products [6,7]. One example of this is the soldering processes of the "Double-POSSUMTM" 3D packaging structure developed by Amkor, the A9 application processor fabricated by Apple or the AMD's graph card made by Hynix [8][9][10]. In this package, the three daughter chips are first interconnected with the larger mother chip in the form of a flip-chip to form the device, before being interconnected with the largest mother chip, then connected to the package substrate and, finally, interconnected with the PCB substrate to complete the package.…”

Material effect on thermal stress of annular-trench-isolated through silicon via (TSV)

“…[10][11][12][13] The large differences in coefficient of thermal expansion (CTE) between metal core and Si substrate induce high thermal stresses at the interfaces, causing cracks and defects between the layer and the substrate. [14][15][16] Especially, the thermal stress around device locations in the Si substrate greatly influences the shape, size, and performance of devices. [17][18][19][20][21] An annular-trench-isolated (ATI) TSV with a Si ring layer between the insulator layer and the metal core was proposed to reduce the thermal stress in the Si substrate in our previous paper (Fig.…”