3D Embedded multi-core: Some perspectives

Clermidy, Fabien; Darve, Florian; Dutoit, Denis; Lafi, Walid; Vivet, Pascal

doi:10.1109/date.2011.5763213

Cited by 26 publications

(11 citation statements)

References 16 publications

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“…The WIOMING Multi-Processor SoC (MPSoC) [4] has been designed, manufactured and tested for demonstrating this new technology. The MPSoC backbone architecture is organized around a 16-router Asynchronous NoC on which programmable units as well as data management units (Data and Configuration Memory -DCM) are connected.…”

Section: Wideio Stackingmentioning

confidence: 99%

3D stacking for multi-core architectures: From WIDEIO to distributed caches

Clermidy

Dutoit

Guthmuller

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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3D stacking has been viewed as a breakthrough solution for increasing performance in multi-core architectures. The hope is to solve some of the main issues in current multicore architectures: external memory pressure and latency; I/O bottleneck; communication power consumption. In this paper, some advances of this field of research are shown, starting with a WIDEIO experience on a real chip for solving DRAM accesses issue. The integration of a 512 bit-width bus is demonstrated in a Network-on-Chip (NoC) multi-core framework and the resulting performance based on a 65nm prototype with 10µm diameter Through Silicon Vias (TSV). The potentiality of 3D scaling thanks to 3D asynchronous Network-on-Chip implementation is then shown. Finally, an innovative 3D stacked distributed cache strategy aimed at lowering memory latency and external memory bandwidth requirements is presented. This new memory partitioning demonstrates the efficiency of 3D stacking to rethink architectures for addressing multi-core scaling challenges.

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Section: Wideio Stackingmentioning

confidence: 99%

3D stacking for multi-core architectures: From WIDEIO to distributed caches

Clermidy

Dutoit

Guthmuller

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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“…Recently, there have been some works of vertical interconnect serialization as one way to reduce the number of TSVs [9], [54]- [57]. Such serialization schemes reduce the number of TSVs, resulting in more efficient core layout across multiple layers due to the reduced routing congestion and increase the fabrication yield with a small impact on the latency.…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

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“…There are many research centers that investigate 3-D integration and are designing complex systems, such as stacking of several memory layers on top of logic, sensors and actuators on top of logic, and multicore systems connected through TSV arrays [5]. The synergy of using 3-D integration and NoC is making possible to shorten communication distances, thus improving performance and ultimately reducing overall power consumption.…”

Section: Introductionmentioning

confidence: 99%

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Todri‐Sanial

Cheng

2016

IEEE Trans. VLSI Syst.

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Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.Index Terms-3-D ICs, clock networks, power and thermal integrity, power delivery networks (PDNs), through-siliconvias (TSVs).

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3D Embedded multi-core: Some perspectives

Cited by 26 publications

References 16 publications

3D stacking for multi-core architectures: From WIDEIO to distributed caches

3D stacking for multi-core architectures: From WIDEIO to distributed caches

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

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