3D IC Integration and 3D IC Packaging

Lau, John H.

doi:10.1007/978-981-16-1376-0_7

Cited by 18 publications

(12 citation statements)

References 55 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another approach for reducing die temperatures for 3D could be to use more sophisticated cooling techniques, such as liquid cooling [16]. Figure 14 shows the impact of increasing the heat transfer coefficient (HTC) from the hardware calibrated data, on the maximum temperature of a F2F 3D stack CPU-on-CPU configuration.…”

Section: Resultsmentioning

confidence: 99%

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Mathur

Chao

Liu

et al. 2020

2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

3D integration technologies are seeing widespread adoption in the semiconductor industry to offset the limitations and slowdown of two-dimensional scaling. High-density 3D integration techniques such as face-to-face wafer bonding with sub-10 µm pitch can enable new ways of designing SoCs using all 3 dimensions, like folding a microprocessor design across multiple 3D tiers. However, overlapping thermal hotspots can be a challenge in such 3D stacked designs due to a general increase in power density. In this work, we perform a thorough thermal simulation study on sign-off quality physical design implementation of a state-of-the-art, high-performance, out-oforder microprocessor on a 7nm process technology. The physical design of the microprocessor is partitioned and implemented in a 2-tier, 3D stacked configuration with logic blocks and memory instances in separate tiers (logic-over-memory 3D). The thermal simulation model was calibrated to temperature measurement data from a high-performance, CPU-based 2D SoC chip fabricated on the same 7nm process technology. Thermal profiles of different 3D configurations under various workload conditions are simulated and compared. We find that stacking microprocessor designs in 3D without considering thermal implications can result in maximum die temperature up to 12°C higher than their 2D counterparts under the worst-case power-indicative workload. This increase in temperature would reduce the amount of time for which a power-intensive workload can be run before throttling is required. However, logic-over-memory partitioned 3D CPU implementation can mitigate this temperature increase by half, which makes the temperature of the 3D design only 6°C higher than the 2D baseline. We conclude that using thermalaware design partitioning and improved cooling techniques can overcome the thermal challenges associated with 3D stacking. This is an accepted version of the IEEE published article presented at IEEE Electronic Components and Technology Conference (ECTC) 2020 http://www.ectc.net.

show abstract

Section: Resultsmentioning

confidence: 99%

Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology

Mathur

Chao

Liu

et al. 2020

2020 IEEE 70th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

show abstract

“…Motivation MEMS chips are an emerging market. Especially the packaging of these chips is considered crucial, because 60% to 80% of the MEMS device costs are packaging [1]. Hence, efficient packaging processes are required.…”

Section: Introduction ( ) H 1 Eadingmentioning

confidence: 99%

Pick and Place of Sensitive Chips with Vacuum-Free Gecomer® Tools

Lorenz,

Ludewig,

Swiecinski

et al. 2024

IMAPSource Proceedings

View full text Add to dashboard Cite

To cope the lack of suitable pick and place methods for sensitive chips, we present a new process using a gripper tool from the company INNOCISE called Gecomer®. The tool, made of polymer pillars, is using Van der Waals forces to create adhesion between the gripping tool and the chip surface. Hence, the tool works without any vacuum. While placing, the Van der Waals interactions are reduced by buckling those pillars resulting in a decreased contact area. The challenge is to find the right parameters to avoid a re-gripping of the chip during the Gecomer®-movement away from the chip. In this paper we present results on the placement accuracy including the reproducibility compared to a standard vacuum tool for different process parameters. For that, we used a pick and place machine with built-in inspection camera to examine the deviation from the target position. It is revealed that both vacuum and polymer gripper have a similar deviation of approx. ±15 μm. Hence, the placing accuracy is not negatively influenced by the Gecomer® tool and depends only on the machine parameters. Furthermore, we analyze the surfaces of the chips, whether there are any residues of the gripping tool. In a first optical inspection, no damages or residues could be found. The new vacuum-free pick and place process has the potential to open new opportunities in the assembly of sensitive (MEMS)- chips regarding reproducibility, accuracy, and process throughput.

show abstract

“…Thus, three-dimensional (3D) micro-nano devices, such as FinFETs, Tri-Gates, and 3D stacked memory devices, are becoming mainstream in the semiconductor industry, benefitting from their compact size and excellent integration. Nowadays, 3D micro-nano structures are widely applied in biomedicine, 1,2 optoelectronic science, 3,4 chip engineering, 5,6 and many other fields. These 3D micro-nano devices are mainly composed of crystals or polymers.…”

Section: Introductionmentioning

confidence: 99%