3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores

Abstract

Abstract-The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, powerefficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.

Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing

“…Although many optical network designs have been proposed, there has been a growing interest focused towards nanophotonic crossbars for their ultra-low-latency, single-hop communication capabilities [4], [5], [7]. Among these designs include Corona, a single full optical crossbar with bundles of waveguides that snake by each tile on the chip.…”

“…Because channel wavelengths are assumed to be generated by an off-chip laser source, there is currently no convenient means of reducing laser power during runtime; static laser power is simply wasted during low traffic loads. Attempts to maximize static laser power utility through dynamic bandwidth allocation and wavelength stealing have been proposed [7], [10]. Bandwidth can easily be reallocated using nanophotonics as wavelengths can be reassigned to network tiles for reading and writing by retuning appropriate ring resonators.…”

“…Using shared waveguides to transport messages between tiles enables the data network to shift bandwidth to priority tiles simply by rerouting wavelengths and retuning ring resonators to ignore or actively listen on certain wavelength channels. The bandwidth allocation algorithm proposed for R-3D-NoC is adopted for use with the CW/CCW architecture [7]. In this algorithm a reconfiguration controller in each group requests link and buffer utilization statistics over a reconfiguration period.…”

“…As clock scaling is pushed to its limitations, and the industry struggles to maintain the rise in computing performance as predicted by Moore's law, researchers have turned to emerging technologies to propel computing to new levels. Among these technologies, nanophotonic interconnects have garnered considerable attention from academic and industry researchers [2]- [7]. Increasing the number of cores placed on a single chip to hundreds or thousands requires a scalable and efficient interconnect architecture to facilitate inter-cache and memory communication.…”

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

“…No distinction is made between different types of traffic, but rather rich connectivity is sought across all layers of the stack. Die stacking allows the integration of different technologies; Morris et al propose a symmetrical 3D optical NoC [41]. Xu et al [51] customize each layer of a 3D NoC through long link insertion.…”