2019
DOI: 10.1002/adma.201902994
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3D Self‐Assembled Microelectronic Devices: Concepts, Materials, Applications

Abstract: www.advmat.de www.advancedsciencenews.com photolithography techniques. New amorphous semiconducting materials are involved in the development of flexible electronics based on high-performance compounds that include organic [82] and inorganic (e.g., copper oxide [83] or indium-gallium-zinc oxide (IGZO) [84] ) semiconductor possessing, for instance, the transparency [85] required in optoelectronic applications. Once fabricated on polymeric ultrathin substrates, these devices offer the flexibility, stretchability… Show more

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Cited by 81 publications
(70 citation statements)
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References 327 publications
(774 reference statements)
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“…Top‐down strategies applied for m‐bots fabrication include physical vapor deposition (direct deposition and glancing angle deposition), roll‐up technique for the fabrication of micro/‐nanotubes and helical microrobots, and 3D printing techniques such as direct laser writing. [ 69 ] The bottom‐up strategies applied for m‐bots fabrication include electrochemical/electroless deposition, wet chemical synthesis, and self‐assembly process. All fabrication methods of the m‐bots will run through the review.…”
Section: Design Of M‐botsmentioning
confidence: 99%
“…Top‐down strategies applied for m‐bots fabrication include physical vapor deposition (direct deposition and glancing angle deposition), roll‐up technique for the fabrication of micro/‐nanotubes and helical microrobots, and 3D printing techniques such as direct laser writing. [ 69 ] The bottom‐up strategies applied for m‐bots fabrication include electrochemical/electroless deposition, wet chemical synthesis, and self‐assembly process. All fabrication methods of the m‐bots will run through the review.…”
Section: Design Of M‐botsmentioning
confidence: 99%
“…[ 37–43 ] In principle, internal stress arises during the vacuum‐deposited nanomembranes. [ 44,45 ] Figure S1, Supporting Information, shows that the sequential vacuum deposition produces tensile stress of 120 MPa at the top layer (interface of the Si–Ge bilayer structure) while a 330 MPa compressive stress arises at the bottom layer (Au–Si interface). The established force field will subsequently drive the layered nanomembrane into a spiral structure.…”
Section: Figurementioning
confidence: 99%
“…First, numerous complex and functional connections are generated from large scale integration, and thus reducing wiring, such as conductive threads, is considered a bottleneck for further development. Second, the areal density of the device should be increased by introducing a speci cally designed architecture or process 16 . In this point of view, it is highly necessary to develop compact and miniaturized electronic systems that are capable of working on a single ber.…”
Section: Main Textmentioning
confidence: 99%