3D stacked buck converter with 15&amp;#x03BC;m thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's

Ishida, Koichi; Takemura, Koichi; Baba, Kyoko; Takamiya, Makoto; Sakurai, Takayasu

doi:10.1109/3dic.2010.5751437

Cited by 13 publications

(8 citation statements)

References 3 publications

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“…Using (7) and (11) it is possible to calculate the losses variation when going from a 1-phase to a 2-phase buck converter. It comes:…”

Section: Two-phase Convertermentioning

confidence: 99%

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A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

Neveu¹,

Allard²,

Martin³

2016

Analog Integr Circ Sig Process

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This paper reviews the state-of-the-art of high switching frequency, integrated DC-DC converters and presents the main trade-offs and challenges emerging from this review. Various converter structures (1phase buck, 2-phase buck, 2-phase coupled buck and 3level converter) are then discussed and analyzed through simulation from a losses point-of-view. Considering the review, the architecture analysis and the technology model, 4 converters are designed for a given set of specifications: 3.3 V to 1.2 V, 280 mA output current at high switching frequency (100-200 MHz) in 40 nm bulk CMOS. A cascode power stage is used in order to enhance power conversion efficiency, and 1-phase and 2phase structures are designed. Post-layout simulation results are presented, showing an efficiency above 90 % for a 2-phase converter. Keywords DC-DC conversion • High frequency • CMOS • State-of-the-art • Low voltage • Buck 1 Introduction Voltage conversion is a key enabler for large digital SoCs (Systems-on-Chip). There is a need to get the converter closer to its load in order to reduce resistive losses through PCB (Printed Circuit Board) traces, enable dynamic voltage scaling for more energy efficient This work is supported by the European Commission through the Seventh Framework Programme (FP7), under the project grant PowerSWIPE No. 318529.

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“…Using (7) and (11) it is possible to calculate the losses variation when going from a 1-phase to a 2-phase buck converter. It comes:…”

Section: Two-phase Convertermentioning

confidence: 99%

“…Comparing losses from (22) for a converter with an optimum coupling factor (calculating using (19)) against the losses of a non-coupled 2-phase converter (11) gives an advantage to the coupled structure. Fig.…”

Section: Two-phase Coupled Convertermentioning

confidence: 99%

A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

Neveu¹,

Allard²,

Martin³

2016

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

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“…The interconnect parasitics such as resistance inductance are reduced. A demonstration of a DC-DC converter implemented this way was shown by the University of Tokyo [44] and Philips Research team [45]. This type of integration benefits from research on high-k dielectrics [46].…”

Section: ) Integration In Power Systems: On-chip (Soc) or In-packagementioning

confidence: 99%

High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

Brunet

Kleimann

2013

IEEE Trans. Power Electron.

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This paper presents the state of the art technologies currently used to produce high density integrated capacitors for power systems on-chip applications. The use of high-k dielectrics and 3D patterning of silicon for reaching high specific capacitance is reviewed. Integrating capacitors monolithically on the active chip or in package of power systems is discussed and solutions are proposed for minimising series resistance and achieving a high level of integration. A technology based on nanolithography and silicon electrochemical etching is then detailed. It is shown that capacitance densities of up to 700 nF/mm² can be obtained with a submicrometer pores array in a relatively limited thickness. The advantages and disadvantages of further decreasing the pore size to nanosize pores (below 100 nm) are discussed.

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“…Due to the difficulty in integrating on-die dense passive components [5] and high voltage-rating transistors in recent CMOS technology, 3D integration is a key opportunity to propose an alternative and efficient way between off-and ondie converters by using a less recent and more compatible technology to integrate active and/or passive components in DC-DC converters [4], [5], [7].…”

Section: Introductionmentioning

confidence: 99%

3D ICs: An opportunity for fully-integrated, dense and efficient power supplies

Pillonnet

Jeanniot

Vivet

2015

2015 International 3D Systems Integration Conference (3DIC)

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With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.

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3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's

Cited by 13 publications

References 3 publications

A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

A review of state-of-the-art and proposal for high frequency inductive step-down DC–DC converter in advanced CMOS

High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

3D ICs: An opportunity for fully-integrated, dense and efficient power supplies

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