3D stacked wide-operand adders: A case study

Abstract

In this paper, we address the design of wideoperand addition units in the context of the emerging ThroughSilicon Vias (TSV) based 3D Stacked IC (3D-SIC) technology. To this end we first identify and classify the potential of the direct folding approach on existing fast prefix adders, and then discuss the cost and performance of each strategy. Our analysis identifies as a major direct folding drawback the utilization of different structures on each tier. Thus, in order to alleviate this, we propose a novel 3D Stacked Hybrid Prefix/Carry-Select Adder with identical tier structure, which potentially makes the manufacturing of hardware wide-operand adders a reality. Such an N -bit carry select adder can be implemented with K identical tier stacked ICs, where each tier contains two N/K-bit fast prefix adders operating in parallel according to the computation anticipation principle. Their carry-out signals are cascaded through TSVs in order to perform the selection of the sums accordingly, which results in a delay with the asymptotic notation of O(log(N/K) + K). To evaluate the practical implications of direct folding and of the hybrid prefix/carry-select approaches we perform a thorough case study of 65 nm CMOS 3D adder implementations for different operand sizes and number of tiers, and analyze various possible design tradeoffs. Our simulations indicate the hybrid prefix/carry-select approach can achieve speed gains over 3D folding based designs of between 29% and 54%, for 512-bit up to 4096-bit adders, respectively. Even though 3D folding requires less real estate, when considering a more appropriate metric for 3D design, i.e., delay-footprint-cost product, the hybrid prefix/carry-select approach substantially outperforms the folding one and provides delay-footprint-cost reductions between 17.97% and 94.05%.

High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders

“…When a partitioning strategy uses this methodology, we refer to it as 3D direct folding. In [23] we classified the 3D partitioning strategies of the carry tree in an N -bit parallel prefix adder, on a K-tier stack, as follows: 1) Stage Folding (SF): the carry-merge cells in each stage are placed on one tier, as suggested in [20], 2) Bit Interleaving (BI): the carry merge cells on each and every K-th column in the prefix graph are placed on the same tier, as suggested in [21], 3) Bit-Slice Folding (BS): the carry merge cells on every N/K consecutive prefix graph columns are placed on the same tier. In addition to these, a fourth type of partitioning strategy can be applied by generalizing the 3-tier modified prefix tree design proposed in [22]: 4) Enhanced Bit Interleaving (EBI): the same folding strategy as Bit Interleaving, with a modified prefix graph to eliminate the sum logic TSVs.…”

“…The 3D Stacked Hybrid Ripple/Carry-select/Prefix Adder (further referred as HRCP), presented in [23], is an uniformsized carry-select adder [28] mapped on an identical-tier 3D Stacked IC structure. Such an N -bit adder is partitioned on a K identical tier stacked IC as depicted in Figure 5a.…”