3D vertical integration technologies for advanced semiconductor radiation sensors and readout electronics

Abstract

The development of 3D vertical integration in the microelectronic industry brings along significant advantages for pixelated semiconductor radiation sensors in cutting-edge scientific experiments at high luminosity particle accelerators and advanced X-ray sources. These applications set very demanding requirements on the performance of sensors and their readout electronics, in terms of pixel pitch, radiation tolerance, signal-to-noise ratio and capability of handling very high data rates. 3D vertical integration of two or more layers with sensors and CMOS devices naturally leads the designer towards extending pixel-level processing functionalities and achieving novel structures where each layer is optimized for a specific function. This paper reviews the efforts towards the development of novel vertically integrated pixel sensors and discusses the challenges that are being tackled to qualify these devices for actual applications. IntroductionNowadays 3D vertical integration technology is already playing an important role in the design of advanced silicon pixel sensors for commercial imaging applications. The performance of imaging devices can be greatly enhanced by the high-density interconnection of two or more layers with CMOS sensor and advanced readout electronics, which can be thinned for backside illumination and tiled to achieve a large area coverage with no dead regions [1].In the past few years, the developments in this field have suggested that 3D integration could bring along a performance leap for semiconductor radiation detectors in future high energy physics experiments at particle accelerators [2]. In these applications, a fundamental problem will be the reconstruction of charged particle tracks with high resolution pixelated sensors. These sensors, along with the readout electronics, will be required to have a small pixel pitch (≤ 20 Pm in some applications), a high degree of radiation tolerance, a large signal-to-noise ratio, a low mass to minimize particle scattering, a low power dissipation and the capability of handling very high data rates. To meet the requirements of these applications, advanced functions have to be performed in the electronics elementary cell of each pixel to cope with signal-to-noise ratio and high data rate requirements. These functions include amplification, filtering, calibration, discriminator threshold adjustment, analog-todigital conversion, zero suppression (also called data sparsification) and time stamping. 3D integration can be a solution to the problem of integrating all these functions inside a small pixel, avoiding the use of aggressively scaled CMOS, below 100 nm feature size, which can be expensive and challenging for analog circuit design.