4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−7 random hardware failures per hour reliability

Takahashi, Chikafumi; Shibahara, Shinichi; Fukuoka, Kazuki; Matsushima, Jun; Yuko, Kitaji; Shimazaki, Yasuhisa; Hara, Hirotaka; Irita, Takahiro

doi:10.1109/isscc.2016.7417916

Cited by 18 publications

(11 citation statements)

References 2 publications

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“…Transient faults are analyzed using fault injection on the SoC board. The proposed fault-tolerance architecture has a fault-tolerant performance with a high fault coverage and low overhead in comparison with previous works [12,16,18,27,28], as depicted in Figure 9.…”

mentioning

confidence: 86%

“…In automotive applications, the processor requires a fault-tolerant feature to prevent the transient faults due to voltage fluctuation, wide temperature variation, and exposure to particle radiation. Moreover, the advanced driver-assistant system (ADAS) processor installed in the vehicle should be extremely robust and stable in its operation to guarantee safety and convenience [12].…”

Section: Introductionmentioning

confidence: 99%

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40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

2020

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The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function‐safe architecture is proposed for a fault‐tolerance system such as an electronics system for autonomous cars. The general‐purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self‐recovering cache and dynamic lockstep function. The function‐safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28‐nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function‐safe design can have ISO26262 ASIL‐D with the single‐point fault‐tolerance rate of 99.64%.

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mentioning

confidence: 86%

Section: Introductionmentioning

confidence: 99%

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

2020

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“…ISO26262 for automotive and IEC61508 for industrial). In this context, proper implementation of security and safety functions in accordance with those standards is one of the key efforts in MCU/SoC products [4], [12], [13] as well as eFlash design for secure data storage and access.…”

Section: Security and Safety Functions For Eflash Sub-systemmentioning

confidence: 99%

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Kimura

Taito

Hidaka

2020

IEICE Trans. Electron.

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Embedded system approaches to edge computing in IoT implementations are proposed and discussed. Rationales of edge computing and essential core capabilities for IoT data supply innovation are identified. Then, innovative roles and development of MCU and embedded flash memory are illustrated by technology and applications, expanding from CPS to big-data and nomadic/autonomous elements of IoT requirements. Conclusively, a technology roadmap construction specific to IoT is proposed.

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“…Overall, instantaneous power demand may surpass the capacity of the PDN, thus leading to a scenario where circuits become underpowered during relatively short time intervals, until the power demand decreases. In such scenario, voltage decreases to levels where correct operation cannot be preserved -often referred to as voltage droops -and actions such as decreasing operating frequency must be taken to decrease power demand and preserve correct operation [12], [28], [4]. While the effect of droops is relatively small in high-performance systems, in critical systems their impact on metrics like worstcase timing and power budgeting can be high.…”

Section: A Power Delivery Network Sizingmentioning

confidence: 99%

“…For power verification, defining appropriate test cases and input vectors is critically important to identify whether (high) power peaks can occur and whether they can occur systematically [13]. Power peaks may lead to sporadic or frequent voltage droops that need lowering speed or stalling execution to preserve correctness [12], [28], [4], hence impacting timing of tasks in general, and real-time tasks in particular. For instance, power peaks may depend on the simultaneous occurrence of a number of events in cores, caches and on-chip interconnects, whose fine-grain control cannot be practically exercised.…”

Section: Introductionmentioning

confidence: 99%

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior

Trilla

Hernández

Abella

et al. 2019

2019 22nd Euromicro Conference on Digital System Design (DSD)

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The verification and validation process of embedded critical systems requires providing evidence of their functional correctness and also that their non-functional behavior stays within limits. In this work, we focus on power peaks, which may cause voltage droops and thus, challenge performance to preserve correct operation upon droops. In this line, the use of complex software and hardware in critical embedded systems jeopardizes the confidence that can be placed on the tests carried out during the campaigns performed at analysis. This is so because it is unknown whether tests have triggered the highest power peaks that can occur during operation and whether any such peak can occur systematically. In this paper we propose the use of randomization, already used for timing analysis of real-time systems, as an enabler to guarantee that (1) tests expose those peaks that can arise during operation and (2) peaks cannot occur systematically inadvertently.

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4.5 A 16nm FinFET heterogeneous nona-core SoC complying with ISO26262 ASIL-B: Achieving 10−7 random hardware failures per hour reliability

Cited by 18 publications

References 2 publications

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior

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