This paper presents the design and measuring of a 6-bit SiGe BiCMOS digital step attenuator, with a maximum attenuation of 31.5 dB, and with 0.5 dB steps (64 states) that have the lowest RMS amplitude error and a low phase variation. To alleviate the large phase variation of the conventional attenuator at a higher frequency, the proposed attenuator utilizes a phase compensation circuit. The phase compensation circuit consists of a 2nd order low pass phase correction network, stacked in parallel to the switched π/T structure of each attenuation module. An attenuator with a phase compensation network shows a root mean square (RMS) amplitude error less than 0.43 dB, and the RMS insertion phase deviation varying from 1.6 • to 4.2 • over 20-24 GHz. The measured insertion loss is 21.9 dB and the input P1dB is 14.03 dBm at 22 GHz. Our confidence regarding the obtained results stems from a comparison of simulations, carried out using Cadence Virtuoso, and physical measurements using a network analyzer (also presented). The proposed attenuator's design has a 0.13 µm SiGe BiCMOS process, with an approximate occupied area of 1.92 × 0.4 mm 2 including chip pads.