4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

Abstract

In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si0.7Ge0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si0.7Ge0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O2 plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si0.7Ge0.3 channel. As a result, the selectivity of Si to Si0.7Ge0.3 can reach 32.84 with a signature of “rectangular” Si0.7Ge0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si0.7Ge0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, Ion/Ioff ratio of 9 × 105 and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under VDS = VGS = −0.8 V due to its large resistance of source and drain (9.2 × 105 Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 104 Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and Ion/Ioff ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

New structure transistors for advanced technology node CMOS ICs

“…Vertically stacked NW GAAFETs with high-mobility SiGe channels were also presented by IMECAS in subsequent years, as shown in Fig. 2(c) [ 32 ].…”

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

“…This reduces the total chip utilization by α 2 . These under-clocked active devices or unused silicon measured as fraction of the total chip is referred to as Dark Silicon [7]. With aggressive scaling this dark silicon increases and could potentially reach in the next few years.…”

Superlattice effects and limitations of non-destructive measurement of advanced Si/Si(1-x)Ge(x) superlattice structures using Mueller matrix scatterometry (MMSE) and high-resolution x-ray diffraction (XRD)

“…3D structures have become necessary due to scaling and performance requirements at advanced process nodes 2,3 . Nanosheet/Nanowire (NS/NW) transistors with vertically stacked channels are one type which use Silicon Germanium Si/Si1-xGex superlattice film stacks to enable selective etch processing to make NS/NW transistors [4][5][6][7] . NS/NW transistors have increased in the number of channels may further evolve into ForkFET and CFET 6 .…”