4-Slot, 8-Drop Impedance-Matched Bidirectional Multidrop DQ Bus With a 4.8-Gb/s Memory Controller Transceiver

Abstract

In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13-µm CMOS process and operates with a 1.2-V supply voltage. Its effectiveness is shown on various multidrop channel configurations. At 4.8 Gb/s, this transceiver with a 4-slot, 8-drop IMBM DQ bus has an eye opening of 0.39 UI in TX mode and 0.58 UI in RX mode, at a threshold of 10 −9 BER, whereas a comparable transceiver with a conventional 4-slot, 8-drop stub series terminated logic has no timing margin under the same test conditions. Our transceiver consumes 14.25 mW/Gb/s per DQ in TX mode, and 13.69 mW/Gb/s per DQ in RX mode.Index Terms-High-speed interface, impedance matching, memory controller, memory interface, memory transceiver, multidrop DQ bus, stubseries terminated logic.

Challenges toward the application of high-speed digital signaling to multi-drop transmission system with reflection compensation lines

“…The characteristic impedance Z = 50 Ω for the main bus line, and a constraint of Z 0 ≤ 85 Ω for the stub line is assumed for practical PCB implementation. By evaluating the objective function (5), the optimal values of Z 0 and R i are deduced by Genetic Algorithm (GA). The results are shown in Table I.…”

“…For another approach, Stub Series Terminated Logic (SSTL) is a method wellknown for DDR SDRAM wiring [5], in which series resistance elements are connected in each stub line to reduce the reflection. The STTL also does not suffer from the issue of reflections, but the drawback is power and amplitude loss due to the resistive elements.…”