40 nm Ultralow-Power Charge-Trap Embedded NVM Technology for IoT Applications

Kouznetsov, Igor; Ramkumar, K.; Prabhakar, V.; Hinh, Long; Shih, Hung-Sheng; Saha, Swatilekha; Govindaswamy, Srikanth; Amundson, M.; Dalton, D.; Phan, Tony T.; Luzada, Z.; Raghavan, Vijay R.; Agrawal, Vimal Kumar; Donnelly, Kevin; Shih, Po-I; Huang, Cece; Lee, K.L.; Wang, C.H.; Huang, Cheng‐Chieh; Lin, C.-H.; Sheu, Yeuan-Ming

doi:10.1109/imw.2018.8388777

Cited by 8 publications

(3 citation statements)

References 5 publications

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“…Table II summarizes the features of the read operations among NVMs. In comparison with the 28 nm SONOS eFLASH, 27) the NBNVM achieves much larger operation voltage range, 54% reduction of the measured read energy 02SP59-3 © 2024 The Japan Society of Applied Physics per bit and 26% reduction of the access time at 1.05 V. Compared to the 28 nm ReRAM with a high-K cell transistor, 26) the NBNVM achieves a 71% reduction in the measured minimum read energy per bit, but it has approximately twice the access time at 0.85 V.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…[18][19][20][21][22][23] A 65 nm MCU with embedded NB non-volatile memory (NBNVM) has achieved dramatically read energy reduction over the designs equipped with the other NVMs. 24) In the conference extended abstract, 25) we developed a 28 nm NBNVM for further performance improvement and demonstrate its superiority by comparisons with a ReRAM 26) and a commercial SONOS (Silicon Oxide Nitride Oxide Silicon) eFLASH 27) at the same technology node. Moreover, we integrated it in a 32 bit RISC-V MCU and showed correct operation by measured waveforms.…”

Section: Introductionmentioning

confidence: 99%

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A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

Bai,

Nebashi,

Miyamura

et al. 2024

Jpn. J. Appl. Phys.

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A 28nm 512Kb NanoBridge non-volatile memory is developed for an energy-efficient microcontroller unit. 0.11pJ/bit read energy is achieved by utilizing an inverter sense scheme thanks to large ON/OFF conductance ratio of a split-electrode NanoBridge. The read energy is 71% and 54% less than those of a ReRAM and a SONOS commercial embedded NOR Flash at the same technology node, respectively. Moreover, a 28nm 32-bit RISC-V microcontroller unit embedded with a 2Mb NanoBridge non-voltage memory is fabricated and achieves 80MHz operation frequency.

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Section: Performance Evaluationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

Bai,

Nebashi,

Miyamura

et al. 2024

Jpn. J. Appl. Phys.

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“…All energy and area estimates are based on SONOS arrays and peripheral circuits that are designed and simulated in an embedded 40nm process compatible with SONOS memory [4,35]. The energy consumption of the array and row drivers is based on the average cell conductances in Fig.…”

Section: Mvm Core Designmentioning

confidence: 99%

On the Accuracy of Analog Neural Network Inference Accelerators

Xiao¹,

Feinberg²,

Bennett³

et al. 2021

Preprint

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Specialized accelerators have recently garnered attention as a method to reduce the power consumption of neural network inference. A promising category of accelerators utilizes nonvolatile memory arrays to both store weights and perform in situ analog computation inside the array. While prior work has explored the design space of analog accelerators to optimize performance and energy efficiency, there is seldom a rigorous evaluation of the accuracy of these accelerators. This work shows how architectural design decisions, particularly in mapping neural network parameters to analog memory cells, influence inference accuracy. When evaluated using ResNet50 on ImageNet, the resilience of the system to analog non-idealities-cell programming errors, analog-to-digital converter resolution, and array parasitic resistances-all improve when analog quantities in the hardware are made proportional to the weights in the network. Moreover, contrary to the assumptions of prior work, nearly equivalent resilience to cell imprecision can be achieved by fully storing weights as analog quantities, rather than spreading weight bits across multiple devices, often referred to as bit slicing. By exploiting proportionality, analog system designers have the freedom to match the precision of the hardware to the needs of the algorithm, rather than attempting to guarantee the same level of precision in the intermediate results as an equivalent digital accelerator. This ultimately results in an analog accelerator that is more accurate, more robust to analog errors, and more energy-efficient.

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