400 Gb/s Real-Time Trials on Commercial Systems for Next Generation Networks

Lavigne, B.; Bertran-Pardo, O.; Bresson, C.; Lefrançois, M.; Balmefrezol, E.; Monnier, M. Le; Raddatz, L.; Suberini, L.

doi:10.1109/jlt.2015.2476697

Cited by 7 publications

(1 citation statement)

References 13 publications

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“…Widely deployed 100-Gb/s-class optical transceivers are implemented using polarization-division-multiplexed QPSK with a symbol rate of 32 GBd [29]. Early solutions for 400 Gb/s per channel were offered by the dual-carrier 32-GBd-class 16QAM signal [30]. Recently, the net rates per wavelength of commercially available transceivers have been increased up to 600 Gb/s using 64-GBd-class 64QAM signals [31], [32], [33] and 800 Gb/s using 100-GBd-class with 16QAM signals [34].…”

Section: Proceedings Of the Ieeementioning

confidence: 99%

Coherent Optical Transceivers Scaling and Integration Challenges

et al. 2022

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The advancement of digital coherent technologies has dramatically increased the system capacity per singlecore single-mode fiber to the point that we can now approach the Shannon limit by utilizing high-order modulation formats and high-coding gain forward error correction (FEC) codes.Because the required energy per bit increases exponentially the closer we get to the Shannon limit, extending the available optical bandwidth by using ultrawideband wavelength-division multiplexing (WDM) and/or spatial-division multiplexing (SDM) is indispensable for increasing the system capacity with high energy efficiency. However, simple extensions of wavelength resources and spatial parallelization dramatically increase the number of transceivers (TxRxs) in proportion to the wavelength/spatial multiplicity. The key to achieving cost-and energy-efficient systems is to reduce the system complexity by using high-density integration and broadband optelectronics.In this article, we overview and discuss the recent advances of coherent optical transceivers integrated with an optical front end and digital signal processing (DSP)/application-specific integrated circuit (ASIC). We then present the transponder architectures and the challenges involved in applying them for massive parallelized transmission systems.

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