45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

Okuno, Masaki; Okabe, Kimiko; Sakuma, T.; Suzuki, Kazumichi; Miyashita, T.; Yao, T.; Morioka, Hiroshi; Terahara, M.; Kojima, Y.; Watatani, H.; Sugimoto, K.; Watanabe, Takashi; Hayami, Y.; Mori, Toshihiko; Kubo, T.; Iba, Y.; Sugiura, Iwao; Fukutome, H.; Morisaki, Yasuhiro; Minakata, H.; Ikeda, Koichi; Kishii, Sadahiro; Shimizu, Naohiro; Tanaka, Tetsu; Asai, S.; Nakaishi, Masafumi; Fukuyama, S.; Tsukune, A.; Yamabe, Masaki; Hanyuu, I.; Miyajima, M.; Kase, M.; Watanabe, K.; Satoh, S.; Sugii, T.

doi:10.1109/iedm.2005.1609264

Cited by 5 publications

(1 citation statement)

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“…A is a fitting coefficient, K √ E is the √ E model field acceleration factor, V str is the stress voltage, and s is the dielectric spacing. [58] There are four major process variables that impact the physical spacing of via chain structures. They are trench and via critical dimensions (CDs) variations, lithography trench-via overlay misalignment (MA), CMP non-uniformity-caused top spacing variation, and line edge roughness.…”

Section: Via Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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Section: Via Width and Space Rulesmentioning

confidence: 99%