5.1 A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications

Xu, Chen; Mo, Yaowu; Ren, Guanjing; Ma, Weijian; Xin, Wang; Shi, Wenjie; Hou, Jinjian; Shao, Ke; Wang, Haojie; Xiao, Pengge; Shao, Zexu; Xie, Xuehui; Wang, Xiaoyong; Yiu, Cky

doi:10.1109/isscc.2019.8662441

Cited by 18 publications

(7 citation statements)

References 4 publications

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“…The 108 MP imager consumes only 551 mW and also achieves a remarkable figure-of-merit (FoM) of 0.71 e - ·nJ based on the common FoM equation for image sensor applications [ 10 ]. In Table 3 , the performance of the 108 MP imager is summarized and compared with previously published works [ 5 , 11 , 12 , 14 , 16 ]. Compared to other image sensors, this work shows a remarkable FoM with a low RN.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

“…As the applications of image sensor systems become more diverse, they require extreme characteristics that are difficult to achieve, such as 200-megapixel (MP) resolution, 140 dB dynamic range, ultra-compact multi-functionality, and invisible ray cameras [ 11 , 12 , 13 ]. Additionally, increased power consumption and heat generation are issues as more image functions are required for high-resolution cameras, such as fast auto-focus (<0.3 s) and slow-motion video with ultra-high frame rates (>240 frames/s) [ 13 , 14 , 15 , 16 ]. Moreover, there has been a recent demand for ultra-low-power characteristics for always-on-display capabilities in imaging systems.…”

Section: Introductionmentioning

confidence: 99%

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A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

Jun

2023

Sensors

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This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor’s operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

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Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

Jun

2023

Sensors

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“…This method, employing only two capacitors for four signals, can be used with many other HDR techniques, including conventional LOFIC, dual exposure, dual gain, etc. Contrary to alternative HDR techniques, which use skimming [21,22], the proposed method does not need FPN calibration, and pipeline readout is possible, improving low-light performance. Figure 8 shows ~90.1 dB DR with ~26.8 dB at the dip point, which is sufficient for many consumer applications such as eye tracking and hand/head tracking.…”

Section: Low Light Signalmentioning

confidence: 99%

A 0.5 MP, 3D-Stacked, Voltage-Domain Global Shutter Image Sensor with NIR QE Enhancement, Event Detection Modes, and 90 dB Dynamic Range

Xhakoni

2023

Sensors

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We introduce a compact voltage-domain global shutter CMOS image sensor for a wide range of applications including consumer, IoT, and industrial applications. With 0.5 MP and 2.79 µm pixels packed in a die size of only 2.3 mm × 2.8 mm, the sensor achieves more than 92% quantum efficiency (QE) in the visible wavelength and more than 36% at near-infrared (940 nm) all while drawing a mere 20 mW at a 10-bit, 30-frame-per-second operational mode. In this article, we focus on the architecture of the sensor and the design challenges encountered to fit all the necessary circuitry in such a limited footprint. Moreover, we detail the new solutions we have developed to meet the demanding specifications of low-power operation and high dynamic range (HDR).

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“…On the other hand, the simplification of the pixel structure is suitable for pixel size reduction; 2.7-μm knee performance global shutter pixel with automatic knee point adjustment [48] and 120-dB 2.2-μm linear-and-logarithmic pixel [49] have been reported for instance.…”

Section: A Nonlinear Response Hdrmentioning

confidence: 99%

HDR CMOS Image Sensors for Automotive Applications

Takayanagi¹,

Kuroda

2022

IEEE Trans. Electron Devices

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Because of various purposes and high dynamic range (HDR) of brightness of objects in automotive applications, HDR image capture is a primary requirement. In this article, HDR CMOS image sensor (CIS) technology and its automotive applications are discussed including application requirements, basic HDR approaches and trends of HDR CMOS image sensor technologies, advantages and disadvantages for automotive application, and future prospect of the HDR technology. LED flicker caused by time aliasing effect and motion artifacts are two major issues in conventional multiple exposure HDR (MEHDR) approach, and several HDR technologies have been introduced for automotive applications. The advancements of image sensor fabrication technology, for instance, backside illumination (BSI) process and pixel level hybrid wafer bonding, have created new trends in the HDR technology.

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5.1 A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications

Cited by 18 publications

References 4 publications

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

A 0.5 MP, 3D-Stacked, Voltage-Domain Global Shutter Image Sensor with NIR QE Enhancement, Event Detection Modes, and 90 dB Dynamic Range

HDR CMOS Image Sensors for Automotive Applications

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