Computers & Electrical Engineering
 2017
DOI: 10.1016/j.compeleceng.2017.06.019
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(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2 +1) unified adder/subtractor with full zero handling

Ghassem Jaberipur
1
,
Armin Belghadr
2
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