53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Mathew, Sanu; Sheikh, Farhana; Kounavis, Michael E.; Gueron, Shay; Agarwal, Amit; Hsu, Steven; Kaul, Himanshu; Anders, Mark; Krishnamurthy, Ram

doi:10.1109/jssc.2011.2108131

Cited by 112 publications

(55 citation statements)

References 10 publications

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“…In the following, the selection of the AES architecture organization and the S-BOX implementation are discussed Area-efficient AES implementations typically adopt folded datapath to reduce the gate count [18]- [21], as opposed to very high-performance targets with higher area cost by an order of magnitude [17]. In area-efficient designs, area tends to be dominated by memory, as shown by the area breakdown in Table I.…”

Section: Design Considerations For Energy-and Area-efficient Aes Corementioning

confidence: 99%

“…1, which summarizes the throughput-energy features of previously published AES prototypes. Previous work focuses either on high throughput [16], [17] or very low-cost designs [18]- [20]. Compared with low-cost designs, the energy/bit of the high-throughput designs can be significantly smaller (down to pico-Joules per bit or even lower) at the cost of larger area penalties.…”

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confidence: 99%

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Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Zhao

Alioto

2015

IEEE Trans. VLSI Syst.

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Near-threshold operation enables high energy efficiency, but requires proper design techniques to deal with performance loss and increased sensitivity to process variations. In this paper, we address both issues with two synergistic approaches. First, we introduce a novel body-biasing technique to mitigate the performance loss at near-threshold voltages while not requiring any additional circuitry for the body-bias control, thereby minimizing the design effort and simplifying the systems-on-chip integration. Second, we introduce a novel statistical design methodology to efficiently and accurately evaluate the design guardband strictly needed in the worst case, thereby keeping the area cost of variations at its very minimum. A 65-nm advanced encryption standard testchip demonstrates 1.65× throughput improvement over a baseline design without body biasing, and enables reliable operation over a wide voltage range (0.5-1.2 V) as opposed to traditional body-biasing schemes. In addition, our testchip achieves 1.63× area efficiency improvement compared with a design based on corner analysis. Accordingly, the proposed techniques are well suited for the design of near-threshold specialized hardware with improved performance, reduced silicon area, and design effort.Index Terms-Advanced encryption standard (AES), energy efficiency, forward body-biasing, near-threshold VLSI circuits, process variations, statistical static timing analysis (SSTA), surrogate timing model.

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Section: Design Considerations For Energy-and Area-efficient Aes Corementioning

confidence: 99%

mentioning

confidence: 99%

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Zhao

Alioto

2015

IEEE Trans. VLSI Syst.

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“…The most efficient one is proposed by Mathew et al [13]. But, their design focused on ASIC platform which cannot directly be ported to FPGA platform.…”

Section: Algorithm 1 Xts Aes Encryption Proceduresmentioning

confidence: 99%

FPGA-based high throughput XTS-AES encryption/decryption for storage area network

Wang

Kumar

2014

2014 International Conference on Field-Programmable Technology (FPT)

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The key issue to improve the performance for secure large-scale Storage Area Network (SAN) applications lies in the speed of its encryption/decryption module. Software-based encryption/decryption cannot meet throughput requirements. To solve this problem, we propose a FPGA-based XTS-AES encryption/decryption to suit the needs for secure SAN applications with high throughput requirements. Besides throughput, area optimization is also considered in this proposed design. First, we reuse the same AES encryption to produce the tweak value and unify the operations of AES encryption/decryption in XTS-AES encryption/decryption. Second, we transfer the computations of AES encryption/decryption from GF (2 8 ) to GF (2 4 ) 2 , which enables us move the map and the inverse map functions outside the AES round. Third, we propose to support the SubBytes and the inverse SubBytes by the same hardware component. Finally, pipelined registers have been inserted into the proposed unrolled architecture for XTS-AES encryption/decryption. The experiments show that the proposed design achieves 36.2 Gbits/s throughput using 6784 slices on XC6VLX240T FPGA.

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“…The S-box circuit is obtained from its truth table synthesis or generation rule when logic-based method is adopted. Although fewer resources are occupied by using two-level logic such as SOP, POS [4], PPRM [5] and BDD [6], or by employing logic circuit to achieve the calculation of the isomorphic fields of GF (2 8 ) (GF ((2 4 ) 2 ) [7] or GF (((2 2 ) 2 ) 2 ) [8]), the logic-base method provides little flexibility for different types of S-box operation. Furthermore, the accumulated resource of different S-box table synthesis should not be overlooked.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers

Yang

Cao

et al. 2016

IEICE Electron. Express

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A LUT with Hierarchical Structure (HS-LUT) is proposed in this paper to realize the unique nonlinear component, Substitution Box (S-box), of the block ciphers. Different types of S-boxes are analyzed and four important features of them are summarized. Then, custom 4R/1W memory is proposed as the storage unit of the reconfigurable S-box, and an example set of block ciphers is put forward to describe how to achieve a satisfactory structure of reconfigurable S-box. The proposed HS-LUT is applicable for different sets of ciphers and it is implemented under TSMC 40 nm CMOS technology to compare with similar work. The comparison result shows that the proposed HS-LUT gains 6.88% to 51.76% area efficiency improvement.

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53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

Cited by 112 publications

References 10 publications

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study

FPGA-based high throughput XTS-AES encryption/decryption for storage area network

An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers

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