6.1 A 1/1.7-inch 20Mpixel Back-illuminated stacked CMOS image sensor for new imaging applications

Abstract

The demand for low-noise (for capturing a clear image in low-light conditions), high-speed (for slow-motion applications and reducing rolling shutter distortion) and high-resolution (for formats beyond 4K) CMOS image sensors is still increasing. In addition, the emerging camcorder market typified by handsfree devices requires the simultaneous capture of still and moving images. To improve noise performance, a method of pseudo-multiple sampling has been proposed [1]. However, the noise reduction effect is insufficient due to the non-uniformity of the CDS period. For high frame rates, multichannel and highdata-rate interfaces have been reported [2][3][4]. For simultaneous capture of still and moving images, a seamless mode change has been shown [5], but it is necessary to convert a still image (full pixel data) to a moving image (2×2 binning data) by an external DSP. This paper presents a 1/1.7-inch 20Mpixel back-illuminated stacked CMOS image sensor with parallel multiple sampling, two simultaneous output streams, and data compression for emerging imaging applications. This sensor realizes: (a) 1.3erms random noise with parallel multiple sampling using double columnparallel ADCs at 20Mpixel 12b 30fps, (b) 16Mpixel readout at 120fps with data compression and a 2.3Gb/s/lane high-speed interface, and (c) two simultaneous output streams of 4Mpixel for Movie mode and 16Mpixel for Still mode. The stacked structure realizes the analog portion of the double column-parallel ADCs supporting parallel multiple sampling and high-speed readout, in addition to the high-level logic circuits.A block diagram of the sensor is shown in Fig. 6.1.1. The sensor consists of a pixel array, the column-parallel single-slope ADCs, an image signal processor with data compression circuits and Scalable Low-Voltage Signaling interface with Embedded Clock (SLVS-EC). Four pixels share a floating diffusion, and two vertical signal lines are assigned to each pixel column. To achieve low-noise and high-speed readout, the sets of two ADCs for each pixel column are located at the top and bottom sides of the pixel array. That is, the number of integrated ADCs is twice the number of columns in the pixel array. The ADC employs a hybrid column counter [2] operating with a 936MHz clock. The speed of the SLVS-EC interface is 2.3Gb/s/lane. Parallel multiple sampling, simultaneous output streaming, and data compression are explained in the following paragraphs.The parallel multiple sampling scheme is realized by a set of two ADCs that consist of two comparators, counters, and DACs. The two ADCs convert the same pixel signal to digital data using Correlated Double Sampling (CDS). The difference of the two conversion timings is ΔT, and each CDS period is the same. The noise performance that results from averaging the uncorrelated data is improved. The measured noise of the parallel multiple sampling scheme is shown in Fig. 6.1.2. The sensor achieves 1.3erms random noise, which is a -3dB improvement vs. normal single sampling, where ΔT is 1.2μs. The power consump...

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