6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology

Ali, Tamer; Chen, E-Hung; Park, Hyun Woo; Yousry, Ramy; Ying, Yu-Ming; Abdul-Latif, Mohammed; Gandara, Miguel; Liu, Chun-Cheng; Weng, Po-Shuan; Chen, Huansheng; Elbadry, Mohammad; Nehal, Qaiser; Tsai, Kun-Hung; Tan, Koan-Sin; Huang, Yen-Hsiang; Tsai, Chung-Hsien; Chang, Yu-Chung; Tung, Yuan-Hao

doi:10.1109/isscc19947.2020.9062925

Cited by 60 publications

(16 citation statements)

References 7 publications

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“…The improvement is attributable to the introduction of an upper limit of 7 on b i (the number of bits allocated to any one sub-channel). The jitter standard deviations, σ j , in our simulations are consistent with recently reported values, such as 150 fs rms in [9] for a 112 Gb/s receiver. If we were to consider transmitter clock jitter, we could include the 140 fs rms reported in [29] for a 112 Gb/s transmitter.…”

Section: Simulation Resultssupporting

confidence: 91%

“…15(a) uses a 25-tap FFE and a 5-tap DFE, significantly more taps than are used in state-of-the-art 4-PAM transceivers. For example, as discussed in Section I, [4], [8], [9] use 2 or fewer DFE taps. Increasing the number of DFE taps to 6 improves the performance slightly ( Fig.…”

Section: B Resultsmentioning

confidence: 99%

“…In some applications, such as memory modules involving a multi-drop bus, reflections cause frequency-domain notches that translate to time-domain "bumps" in the impulse response [6], further complicating DFE. Since DFE complexity increases geometrically with the number of taps [7], modern transceivers tend to keep the number of DFE taps very low (e.g., 2 or fewer) [4], [8], [9] and include a long FFE at the transmitter and/or receiver. However, it is not clear such an approach will work at the higher channel losses expected in 200+ Gb/s links.…”

Section: Introductionmentioning

confidence: 99%

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A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s

Vatankhahghadim

Wary

Bailey

et al. 2021

IEEE Open J. Circuits Syst.

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To overcome the severe losses beyond 28 GHz in low-cost electrical channels, 4-level pulseamplitude modulation (4-PAM) wireline links targeting 112 Gb/s incorporate resource-or power-intensive equalization schemes such as decision-feedback equalizers (DFE) with many taps. Alleviating the timing constraints that cause DFEs to balloon in size and power, discrete multitone (DMT) modulation involves independent sub-channels that can be equalized in the frequency domain without feedback. DMT allows flexibility in assigning bits to each sub-channel, thereby potentially avoiding lossy parts of the frequency spectrum. This article presents behavioural modeling results and an experimental setup used to study DMT transceivers. Our simulations show 200 Gb/s operation at a bit error rate (BER) of less than 10 −5 over an IEEE P802.3ck channel with 21 dB of loss at 50 GHz and assuming 150 fs rms of jitter, 1.26 mV rms of noise at the receiver's input, and 7-bit 80 GS/s data converters. An updated bit-loading algorithm led to BER values 1-2 orders of magnitude below our previous results. The estimated power and area of the associated digital signal processing are comparable to those of DFE. We also present an experimental DMT setup achieving 61.6 Gb/s at a BER of 8.6 × 10 −4 over a physical channel with severe notches that is very challenging for 4-PAM. INDEX TERMS Digital modulation, digital signal processing (DSP), discrete multitone (DMT), transceivers, wireline communication.

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Section: Simulation Resultssupporting

confidence: 91%

Section: B Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s

Vatankhahghadim

Wary

Bailey

et al. 2021

IEEE Open J. Circuits Syst.

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“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

Section: Interconnectmentioning

confidence: 99%

Today’s computing challenges: opportunities for computer hardware design

Bae

2021

PeerJ Computer Science

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Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and interconnect) have started facing their limits, and therefore are not as effective as they used to be and are also expected to reach the end in the near future. Evidently, it is a large challenge for computer hardware industry. However, at the same time it also provides great opportunities for the hardware design industry to develop novel technologies and to take leadership away from incumbents. This paper reviews the technical challenges that today’s computing systems are facing and introduces potential directions for continuous advancement of computing capability, and discusses where computer hardware designers find good opportunities to contribute.

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“…At the chip level, this demand translates to higher bandwidth per wireline channel connecting two adjacent microchips on the same board or on daughter boards sharing the same backplane. Today, research papers report data rates of 112Gb/s/channel [1], [2] and pursue innovations to double this data rate.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Salinas

Cosson-Martin

Laghaei

et al. 2021

IEEE Open J. Circuits Syst.

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Limits of data rate over a wireline channel depend on the channel characteristics, the signaling or modulation scheme, and the complexity one can afford for its implementation. This article compares two signaling schemes, namely baseband and discrete multi-tone (DMT), for two example channels, one with a smooth frequency response and one with a notch frequency response, to examine how far each can push the data rate towards the maximum achievable data rate, derived from Shannon Capacity formula. INDEX TERMS Discrete multi-tone (DMT), pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), Shannon's capacity, bit loading, salz SNR, integrated crosstalk noise (ICN), insertion loss (IL).

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6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology

Cited by 60 publications

References 7 publications

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s

Today’s computing challenges: opportunities for computer hardware design

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

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