6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Sun, Hongbin; Zhang, Yinhang; Yang, Xi

doi:10.1587/elex.19.20220429

Cited by 4 publications

(5 citation statements)

References 29 publications

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“…The HF compensation circuit is illustrated on the left, which is a conventional CTLE with capacitive degeneration and inductive peaking techniques. Like a conventional CTLE [9], the high-frequency gainboosting can be tuned by adjusting the control voltages of degeneration resistor and capacitor in the left part. Fig.…”

Section: Ctlementioning

confidence: 99%

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A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

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Aiming at the jitter issue in four-level pulse amplitude modulation (PAM4) receive link, the key causes related to the non-ideal effects of channel and data decision were analyzed, and a modified PAM4 receiver architecture was proposed. An analog equalizer with extra mid-frequency compensation and 1-tap decision-feedback equalizer were incorporated to minimize the inter-symbol interference. To alleviate the timing constraints in DFE, the feedback loop of slicer was optimized. The post-simulation results based on TSMC 28 nm CMOS process indicate that the proposed 50 Gb/s PAM4 receiver functions well over a channel with 12 dB loss at Nyquist frequency. The peak-to-peak jitters of two restored NRZ signals are 1.5 ps and 2.5 ps, respectively.

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Section: Ctlementioning

confidence: 99%

“…Due to the non-ideal effects of channel, it causes significant attenuation of the transmitter data at high frequencies [9,10,11]. [12] adopts a CTLE with adjustable DC gain to compensate the high frequency loss.…”

Section: Introductionmentioning

confidence: 99%

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Lv,

Xie,

Qin

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In Sun et al (2022), the authors proposed a method to enhance the rate range and reduce power consumption in high-speed serial links by utilizing an adaptive continuous time linear equalizer (CTLE) and a half-rate decision feedback equalizer (DFE) with a hybrid filter and a current-integrating summer. The system was tested using 10 Gb/s PRBS7 signals transmitted through an 18inch FR4 backplane, and the post-simulation results demonstrated a rate range of 6.25-10 Gb/s with excellent performance.…”

Section: High-speed Communication Transmissionmentioning

confidence: 99%

Advances on intelligent algorithms for scientific computing: an overview

et al. 2023

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The field of computer science has undergone rapid expansion due to the increasing interest in improving system performance. This has resulted in the emergence of advanced techniques, such as neural networks, intelligent systems, optimization algorithms, and optimization strategies. These innovations have created novel opportunities and challenges in various domains. This paper presents a thorough examination of three intelligent methods: neural networks, intelligent systems, and optimization algorithms and strategies. It discusses the fundamental principles and techniques employed in these fields, as well as the recent advancements and future prospects. Additionally, this paper analyzes the advantages and limitations of these intelligent approaches. Ultimately, it serves as a comprehensive summary and overview of these critical and rapidly evolving fields, offering an informative guide for novices and researchers interested in these areas.

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“…The data-traffic explosion driven by cloud computing, 5G networks, industrial IoT, and virtual reality has accelerated the demand for high-speed SerDes transceivers to provide massive data throughput [1,2,3,4,5,6,7,8]. Previous studies have demonstrated that four-level pulse amplitude modulation (PAM-4) is superior to non-return-to-zero (NRZ) for the 56∼112-Gb/s serial data communications due to its doubled spectral efficiency, halved Nyquist frequency, and relaxed clock speeds [9,10,11,12,13,14,15].…”

Section: Introductionmentioning

confidence: 99%

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

Xu,

Zheng,

Wang

et al. 2024

IEICE Electron. Express

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This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which a 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced preemphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, and naturally consumes less power as it boosts only the desired symbols. The FS-based pre/post1 taps equalize the high-frequency loss, provide a wide compensation range beyond the Nyquist frequency, and realize a flexible equalization capability, while the BS-DE-based post2 tap compensates for the low-frequency channel loss. Fabricated in a 28-nm CMOS process, the 64-Gb/s transmitter obtains a differential output swing of 1.4 V ppd with an energy efficiency of 1.53 pJ/bit.

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6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Cited by 4 publications

References 29 publications

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

Advances on intelligent algorithms for scientific computing: an overview

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

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