6.3L: Late-News Paper: Fast Addressing of Plasma Display Panels

Abstract

The dynamics of the address discharge and the mechanism behind it are being analyzed. Based on this analysis a novel addressing waveform using low‐voltage addressing drivers and leading to a significant reduction of the overall panel addressing time is being proposed. 3D PIC/Monte‐Carlo simulations of the address discharge in a PDP cell have shown that for certain cell geometries the addressing time of up to 600‐800ns per line can be achieved.