60 pW 20 μm size CMOS implementation of an actual soma membrane

Szczęsny, Szymon; Huderek, Damian

doi:10.1007/s10825-019-01431-2

Cited by 4 publications

(3 citation statements)

References 27 publications

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“…There are different structures of spiking neurons implemented using semiconductor technologies [ 6 , 35 , 36 ]. According to the best knowledge of the authors of this article, implementations of the lowest complexity require using six field-effect transistors and two capacitors [ 7 ] or 15 transistors without a capacitor [ 41 ]. As for the implementation of synapses, due to the current mode, the multiplication operations are performed using circuits with reconfigurable current mirrors [ 42 ], which also makes it possible to invert the current flow direction, and thus also the implementation of negative weights.…”

Section: Discussionmentioning

confidence: 99%

“…The cost of implementing such synapses is four transistors. The cost of implementing the entire SNN 20-1 network with ACC = 1 described in the previous section was 1338 transistors and 62 capacitors in the case of CMOS neurons of type [ 7 ] or 1527 transistors and 20 capacitors in case of CMOS neurons of type [ 41 ]. For comparison, the implementation of a 1 bit digital multiplication operation requires using 48 transistors [ 43 ].…”

Section: Discussionmentioning

confidence: 99%

“…This means that a single weight implemented with a 32 bit precision requires using 1536 transistors, while the entire SNN was implemented using a similar amount of resources. We estimated the parameters of a semiconductor implementation of a network of type [ 41 ] with the 20-1 architecture. The analysis was performed using the TSMC 65 nm technology and the Eldo simulator.…”

Section: Discussionmentioning

confidence: 99%

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Spiking Neural Network with Linear Computational Complexity for Waveform Analysis in Amperometry

Szczęsny

Huderek

Przyborowski

2021

Sensors

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The paper describes the architecture of a Spiking Neural Network (SNN) for time waveform analyses using edge computing. The network model was based on the principles of preprocessing signals in the diencephalon and using tonic spiking and inhibition-induced spiking models typical for the thalamus area. The research focused on a significant reduction of the complexity of the SNN algorithm by eliminating most synaptic connections and ensuring zero dispersion of weight values concerning connections between neuron layers. The paper describes a network mapping and learning algorithm, in which the number of variables in the learning process is linearly dependent on the size of the patterns. The works included testing the stability of the accuracy parameter for various network sizes. The described approach used the ability of spiking neurons to process currents of less than 100 pA, typical of amperometric techniques. An example of a practical application is an analysis of vesicle fusion signals using an amperometric system based on Carbon NanoTube (CNT) sensors. The paper concludes with a discussion of the costs of implementing the network as a semiconductor structure.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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Spiking Neural Network with Linear Computational Complexity for Waveform Analysis in Amperometry

Szczęsny

Huderek

Przyborowski

2021

Sensors

Self Cite

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Explainable spiking neural network for real time feature classification

Szczęsny

Huderek

Przyborowski

2021

Journal of Experimental & Theoretical Artificial Intelligen

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A Reconfigurable Graphene-Based Spiking Neural Network Architecture

Wang

Laurenciu

Cotofana

2021

IEEE Open J. Nanotechnol.

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To explore and enrich the potential of graphene-based neuromorphic computing, we propose a reconfigurable graphene-based Spiking Neural Network (SNN) architecture and a training methodology for initial synaptic weight values determination. The proposed graphene-based platform is flexible, comprising a programmable synaptic array which can be configured for different initial synaptic weights and plasticity functionalities and a spiking neuronal array, onto which various neural network structures can be mapped according to the application requirements and constraints. To reconfigure the proposed graphene-based platform for a practical application, an SNN topology tailored for the application and an initial SNN state (initial synaptic weights, plasticity type), which can be determined by proposed training methodology are required. To demonstrate the validity of the synaptic weights training methodology and the suitability of the proposed SNN architecture for practical utilization, we consider applications, i.e., character recognition and edge detection. In each case, the graphene-based platform is configured as per the application tailored SNN topology and initial state and SPICE simulated to evaluate its reaction to the applied input stimuli. For the first application, a 2-layer SNN with 30 neurons is used to reconfigure the proposed graphene-based architecture and perform character recognition for 5 vowels, i.e., "A", "E", "I", "O", and "U" variations. Our simulation indicates that the graphene-based SNN can achieve up to 94.5 % recognition accuracy for the considered test datasets, which is comparable with the one delivered by a functionally equivalent Artificial Neural Network (ANN). Further, we reconfigure the architecture for a 3-layer 13 neurons SNN to perform edge detection on 2 grayscale images, Lena and Cameraman. SPICE simulation results indicate that the edge extraction results are close agreement with the one produced by classical edge detection operators, i.e., Canny, Roberts, Sobel, and Prewitt, in terms of visual perception, Peak Signal-to-Noise Ratio (PSNR), and Mean Squared Error (MSE). Our results demonstrate that the graphene SNN platform is able to properly perform character recognition and edge detection tasks, which suggests the feasibility and flexibility of the proposed approach for various application purposes. Moreover, the utilized graphene-based synapses and neurons operate at low supply voltage (200 mV), consume low energy per spike for both neuron (43 pJ and 5.2 × 10 −7 pJ at 200 Hz and 20 GHz spike frequency scale, respectively) and synapse (5.1 pJ and 6.0 × 10 −8 pJ at 200 Hz and 20 GHz spike frequency scale, respectively), and a graphene-based synapse occupies an active area of ≈45 nm 2 (2 GNR devices) and a neuron an active area of ≈176 nm 2 (6 GNR devices), which are desired properties for large-scale energy-efficient implementations.

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60 pW 20 μm size CMOS implementation of an actual soma membrane

Cited by 4 publications

References 27 publications

Spiking Neural Network with Linear Computational Complexity for Waveform Analysis in Amperometry

Spiking Neural Network with Linear Computational Complexity for Waveform Analysis in Amperometry

Explainable spiking neural network for real time feature classification

A Reconfigurable Graphene-Based Spiking Neural Network Architecture

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