60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

Hsieh, Hsieh-Hung; Wu, Po-Yi; Jou, Chewn-Pu; Hsueh, Fu-Lung; Huang, Guo–Wei

doi:10.1109/rfic.2011.5940665

Cited by 43 publications

(23 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because the cascade CS topology can offer better isolation and higher gain compared to the CG or CS topologies [16], and features simultaneous impedance and noise matching, we adopt this two-stage current-reuse cascade topology instead of a three-stage one in order to reduce power consumption and save chip area [4]. The proposed ultra-wideband LNA is implemented in 65 nm RFCMOS technology.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…In the last few years, an unlicensed frequency band ranging from 57 to 64 GHz has attracted great attention, which offers much wider bandwidth and less potential interferes [2,4,9]. Many CMOS circuits and sub-systems designed for this band have been reported in recent literatures [2][3][4]8,9].…”

Section: Introductionmentioning

confidence: 99%

“…Many CMOS circuits and sub-systems designed for this band have been reported in recent literatures [2][3][4]8,9]. However, the design of low cost and highperformance RF circuits and systems within this frequency range is still challenging.…”

Section: Introductionmentioning

confidence: 99%

“…For the application at the 60 GHz frequency band with more than 10 GHz bandwidth, the design becomes even more challenging. Many high-performance low noise amplifiers with ultra-wideband performance at mm-wave range have been presented in recent years [3,4,8,9]. However, it is still of great interest to design a LNA maintaining a balanced performance among low power, flat gain and low noise over an ultra-wideband frequency range.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Feng

et al. 2015

Circuits Syst Signal Process

View full text Add to dashboard Cite

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a currentreused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the currentreused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum S 21 gain of 11.4 dB gain with a −3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the Circuits Syst Signal Process measured S 11 and S 12 are less than −10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.

show abstract

Section: Circuit Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Feng

et al. 2015

Circuits Syst Signal Process

View full text Add to dashboard Cite

show abstract

“…In [6], a T-type matching network is placed between the CS and CG stage to solve the influence of the parasitic capacitance. In [7], an additional inductor was added at the gate of the CG transistor to improve the gain with penalty in the stability of the circuit. In [8], Terry Yao, et al have been explored the algorithmic design methodology of MMW LNA, however their analysis on the interstage match between the CS and CG amplifier was not reasonable, and it was not satisfied with a gain of 14.6 dB, reverse isolation of 32 dB and 3-dB bandwidth of 8 GHz in their work.…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of a V-band low-noise amplifier in 90 nm CMOS for 60 GHz applications

Feng

Guo

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

A V-band low-noise amplifier with the gain boosting and noise reduction technique in 90 nm LP CMOS is implemented and tested in this paper. The operation principles of the two techniques are analyzed in detail. The fabricated LNA has a peak gain of 19.8 dB, 3-dB bandwidth of 10.5 GHz and NF of 5.86 dB at 61.5 GHz. Additionally, the reverse isolation of this LNA is better than 50 dB at all frequency. The input and output return losses are both below −10 dB in the China's 60 GHz unlicensed band (59-64 GHz). The total chip size is 0.36 mm 2 including testing pads.

show abstract

Planar circuit analysis of ultra‐wideband millimeter‐wave inductor using transmission line sections

Ashrafian

Mohammad-Taheri

Naser-Moghaddasi

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

Regarding the capacitive nature of input/output impedances of millimeterwave amplifiers, it is necessary to utilize wideband inductive elements for the design of input/output impedance matching circuits. In this paper, the design and optimization of an ultra-wideband transmission line inductor with an inductance of less than 100 pH are introduced for using at frequencies above 50 GHz. The reason of using this inductor is its superior performance compared to that of a spiral inductor and single-coil inductor. The inductor consists of three rectangular microstrip line segments with nonequal and variable characteristic impedances. The design is done by calculating the impedance matrix using planar circuit analysis (PCA) based on a planar waveguide model, segmentation/desegmentation methods, and an intelligent algorithm in MATLAB. With this design method, the effect of discontinuities, fringing fields at the edges of the microstrip, and the conductor as well as dielectric losses can be considered while minimizing the dispersion effect. In this study, to reduce the calculation time of the impedance matrix, the doubly infinite series are reduced to a singly infinite series by summing the inner sum for a rectangular segment whose one side is shorted and three other sides are open.

show abstract

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

Cited by 43 publications

References 3 publications

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

Analysis and design of a V-band low-noise amplifier in 90 nm CMOS for 60 GHz applications

Planar circuit analysis of ultra‐wideband millimeter‐wave inductor using transmission line sections

Contact Info

Product

Resources

About