65 GHz small-signal-bandwidth switched emitter follower in InP heterojunction bipolar transistors

Abstract

Performances of two switched emitter follower structures for large bandwidth applications have been optimised, compared, implemented and measured. These circuits have been fabricated with a 320 GHz-F T InP double heterojunction bipolar transistor process. Measurements in track mode show a small-signal bandwidth over 65 GHz for one structure and over 50 GHz for the other. Track mode SFDR measured for 500 mV PP up to 15 GHz signal input is greater than 45 dBc.Introduction: High sampling frequency and linear ADCs are of interest for several applications such as the optical, wireless and military communication industries. Recent ADCs most often use track and hold amplifiers (THAs) input interface. These THAs need a large bandwidth, a good linearity, a high sampling rate with an excellent isolation and low losses during hold mode. The switched emitter follower (SEF), which is the main block of the THA, defines these performances.A 40 GHz small-signal-bandwidth two-stage-InP-SEF with an isolation of 25 dB and a 42 GHz small-signal-bandwidth SiGe-THA based on a classic SEF were proposed in [1] and [2], respectively. Different SEF architectures used in a 16 GHz small-signal-bandwidth SiGe THA were reported in [3].In this Letter we present two different large bandwidth InP-DHBT SEF circuits: a two-stage SEF structure and a single-stage SEF structure followed by an emitter follower (EF). Analysis of hold mode isolation is followed by comparison of measurements and simulation results of both circuits in track and hold mode.

70 GSa/s and 51 GHz bandwidth track‐and‐hold amplifier in InP DHBT process

“…1. This THA is based on a 55 GHz bandwidth double‐stage SEF structure proposed in [5]. The circuit is fully differential and composed of a degenerated Cherry‐Hooper input buffer, two SEFs (for differential operation) each with a pseudo capacitor to cancel the off‐state base–emitter transistor capacitance, a degenerated differential pair as an output buffer and a clock buffer which provides the clock signals to the SEFs.…”

“…The layout has been optimised to obtain the best circuit decoupling and to keep the differential architecture benefit. The circuit was fabricated in the 320 GHz f T InP DHBT technology used in [5] to design the SEFs.…”

“…70 GHz sampling rate was the maximum available frequency for our laboratory signal synthesisers. Conclusion: A fully differential THA with a double-stage SEF [5] based core has been realised in a 320 -GHz-f T InP DHBT technology. The circuit was characterised in both track mode and track-and-hold mode in the frequency and in time domains.…”

A 60 GSa/s InP-DHBT-THA with 50 GHz Bandwidth for High Bit Rate Communication Systems

“…To reduce the feedthrough, a pseudo-capacitance C FF (Fig. 1) is used in order to cancel the off-state base-emitter transistor capacitance [4].…”