65 nm HR SOI CMOS Technology: emergence of Millimeter-Wave SoC

Abstract

Today, measurement of 65 nm CMOS [1] and 130nm-based SiGe HBTs [2] technologies demonstrate both F T (current gain cut-off frequency) and Fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100 nm III-V HEMT. Consequently, the integration of full transceiver at 60 GHz has been achieved both in SiGe bipolar [3] and CMOS technology [4].In the same time passive circuits working @ 220 GHz have been achieved and characterized on High Resistivity SOI demonstrating state-of-the-art performances and good agreement with electrical simulations using developed models. Moreover, HR SOI has also demonstrated some advantages concerning the performances of integrated antennas [5] and a first fully integrated prototype with amplifier, filter and antenna has already been achieved using STMicroeletronics 130 nm CMOS HR SOI technology [6]. This paper will review the MMW performances of STMicrolectronics 65 nm CMOS HR SOI technology from device up to circuit level and discuss the opportunities of MMW SoC integrated on CMOS HR SOI technology.

65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

“…We present a 65nm RF SOI CMOS technology, targeted as Low Power (LP) to serve mobile applications. The integration has been made on 300mm SOI wafers with a High Resistive (HR) back substrate (> 1kOhm-cm) to improve RF performances [1,2]. The initial SOI film thickness is 70nm on top of a 145nm thick oxide (see cross section in Figure 1).…”

“…

We present a 65nm RF SOI CMOS technology, targeted as Low Power (LP) to serve mobile applications. The integration has been made on High Resistive (HR) back substrate 300mm SOI wafers from SOITEC to improve performances in high frequency range, compared to bulk [1,2]. For the first time, low leakage SRAM (Isb< 10pA at 0.9V, 25°C, for 0.62µm 2 and 0.52µm 2 cells) are integrated on these HR wafers, and the paper reports a 30% power reduction in operation for a given maximum speed, compared to similar SRAM design on bulk.

…”