65nm Low Power Digital to Analog Converter for CUWB

Chander, Kailash; Choudhry, Sudhanshu

doi:10.1109/icoei.2018.8553815

Cited by 4 publications

(1 citation statement)

References 10 publications

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“…Hence, at the time of application of the synapse output waveform, a digital-to-analog converter (DAC) is required (Table IV). The DAC is a complex mixed signal circuit whose power (500 𝜇W for 4-bit and 0.25 𝜇m node) and area (~ 1500 𝜇m 2 ) scale badly with number of bits as may be the requirement for a high-fidelity reconstruction of the desired waveform [40]- [42] (Table V). A 0 th order synapse or a rectangular pulse of finite width, on the other hand, is much easier to implement using binary levels digital counters comprising of simple flip-flops (~ 20 transistors per flip-flop) with minimal circuit complexity (500 𝜇m 2 for 4-bit i.e., around 80-100 transistors in 0.25 𝜇m node) and power consumption (5 𝜇W -estimated as 50X (same as size ratio) with the inverter pair dynamic power) [39].…”

Section: B Benefits For Mixed-signal Implementationmentioning

confidence: 99%

Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

Saraswat

Gorad

Naik

et al. 2021

2021 International Joint Conference on Neural Networks (IJCNN)

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Liquid State Machines are brain inspired spiking neural networks (SNNs) with random reservoir connectivity and bio-mimetic neuronal and synaptic models. Reservoir computing networks are proposed as an alternative to deep neural networks to solve temporal classification problems. Previous studies suggest 2 nd order (double exponential) synaptic waveform to be crucial for achieving high accuracy for TI-46 spoken digits recognition. The proposal of long-time range (ms) bio-mimetic synaptic waveforms is a challenge to compact and power efficient neuromorphic hardware. In this work, we analyze the role of synaptic orders namely: 𝜹 (high output for single time step), 0 th (rectangular with a finite pulse width), 1 st (exponential fall) and 2 nd order (exponential rise and fall) and synaptic timescales on the reservoir output response and on the TI-46 spoken digits classification accuracy under a more comprehensive parameter sweep.We find the optimal operating point to be correlated to an optimal range of spiking activity in the reservoir. Further, the proposed 0 th order synapses perform at par with the biologically plausible 2 nd order synapses. This is substantial relaxation for circuit designers as synapses are the most abundant components in an in-memory implementation for SNNs. The circuit benefits for both analog and mixed-signal realizations of 0 th order synapse are highlighted demonstrating 2-3 orders of savings in area and power consumptions by eliminating Op-Amps and Digital to Analog Converter circuits. This has major implications on a complete neural network implementation with focus on peripheral limitations and algorithmic simplifications to overcome them.

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Section: B Benefits For Mixed-signal Implementationmentioning

confidence: 99%

Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

Saraswat

Gorad

Naik

et al. 2021

2021 International Joint Conference on Neural Networks (IJCNN)

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Pr x Ca 1 − x MnO 3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem

et al. 2019

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The neural network enables efficient solutions for Nondeterministic Polynomial-time (NP) hard problems, which are challenging for conventional von Neumann computing. The hardware implementation, i.e., neuromorphic computing, aspires to enhance this efficiency by custom hardware. Particularly, NP hard graphical constraint optimization problems are solved by a network of stochastic binary neurons to form a Boltzmann Machine (BM). The implementation of stochastic neurons in hardware is a major challenge. In this work, we demonstrate that the high to low resistance switching (set) process of a PrxCa1−xMnO3 (PCMO) based RRAM (Resistive Random Access Memory) is probabilistic. Additionally, the voltage-dependent probability distribution approximates a sigmoid function with 1.35%–3.5% error. Such a sigmoid function is required for a BM. Thus, the Analog Approximate Sigmoid (AAS) stochastic neuron is proposed to solve the maximum cut—an NP hard problem. It is compared with Digital Precision-controlled Sigmoid (DPS) implementation using (a) pure CMOS design and (b) hybrid (RRAM integrated with CMOS). The AAS design solves the problem with 98% accuracy, which is comparable with the DPS design but with 10× area and 4× energy advantage. Thus, ASIC neuro-processors based on novel analog neuromorphic devices based BM are promising for efficiently solving large scale NP hard optimization problems.

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High Throughput Circuit Designs of Digital to Analog Converter

Anjaneya,

2023

2023 5th International Conference on Recent Advances in Information Technology (RAIT)

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65nm Low Power Digital to Analog Converter for CUWB

Cited by 4 publications

References 10 publications

Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

Hardware-Friendly Synaptic Orders and Timescales in Liquid State Machines for Speech Classification

Pr x Ca 1 − x MnO 3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem

High Throughput Circuit Designs of Digital to Analog Converter

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