65nm OPC and design optimization by using simple electrical transistor simulation

Abstract

In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance: 1)A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects. 2)Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples:-design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor. -Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.

Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices

“…Several methods have been proposed for 2D shaped device effects [3], but none of them takes into account the non-uniform current density distribution through the device. These models also tend to be threshold voltage-based, which makes calibrating to silicon difficult due to the ambiguous nature of defining the threshold voltage [7], [8]. Our current density model is based directly on currents and can thus be easily calibrated to silicon data or SPICE models.…”

32-nm SOC printing with double patterning, regular design, and 1.2 NA immersion scanner

“…The exercise has been completed at 45nm because design maturity is higher than 32nm and OPC simulation is well representative of the final technology. Effective width (Weff) and length (Leff) of the transistor have been calculated using a similar method to one presented in a previous paper [2]. Four different styles of regular cell have been evaluated for length effect and three for width effect.…”

Impacts of optical proximity correction settings on electrical performances

“…These works mostly apply two approaches to model the non-rectangular transistors using SPICE simulators and compact transistor models. The modeling approaches include dividing each non-rectangular poly gate into a number of narrow-sliced transistors of varying gate length in parallel [2][6][9] [11], and approximating each non-rectangular transistor with an equivalent rectangular transistor [13][14] [15]. However, the former approach suffers from the lack of accurate models for narrow-width transistors and may increase the simulation time if the circuit is large and complex.…”

“…There have been many literatures which discuss the impacts of distorted device images on device characteristics and circuit performances [2][3] [6] [7][8] [9] [13], layout optimization, and design rule trade-off [11] recently. These works mostly apply two approaches to model the non-rectangular transistors using SPICE simulators and compact transistor models.…”