8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS

Abstract

As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1][2][3][4][5]. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range. Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands. In the presence of input jitter and phase-detector (PD) non-idealities, it is difficult to design an architecture where the resolution of the capacitor bank and the turnoff mechanism can guarantee that the VCO frequency will eventually fall within the pull-in range of the CDR. This paper introduces a full-rate reference-less CDR architecture with neither an FD nor a lock detector. Its operation is instead based on the theory that if an offset (or "strobe point") is deliberately introduced into the PD characteristic, the pull-in range will be enhanced as long as the initial frequency offset is the appropriate polarity [6]. For example, if the strobe point (SP) is negative as illustrated in curve (b) of Fig. 8.8.1 and the initial VCO frequency is higher than the input data bit rate, then the VCO frequency will naturally decrease toward the correct frequency since there will be a net discharge of the loop filter during each cycle slip compared with the ideal case as shown in curve (a) of Fig. 8.8.1. Therefore, the linear PD itself can function as an FD with a very high capture range if the polarity of the SP is set appropriately, consistent with the initial VCO frequency.The CDR architecture used to implement this concept is shown in Fig. 8.8.2. Other than those in the digital control circuit (DCC), all signals are differential. The SP of the PD is controlled by voltage V SP , which is generated by the DCC. A frequency-acquisition algorithm is used to set the polarity of the SP and search the correct band in the capacitor bank while in the frequency-acquisition mode (FAM). The resolution of the capacitor bank is only 5 bits, since the "singlesided" pull-in range is sufficiently wide and the requirement for the tuning range in each band does not need to be very stringent.The combined phase detector/strobe point detector (SPD) circuit is shown in Fig. 8.8.3. DFF1, DFF2, BUF1, XOR1, and XOR2 compose a standard Hogge PD. By inserting the two tunable buffers BUF2 and BUF3, the value of the SP can be adjusted overall range of ±15ps by changing the difference between their delays vi...

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits

“…Reg[0] Reg [1] Reg [3] Reg [2] Reg [4] Fup1 serious as time passes. The outflow for the coarse voltage would increase Vfine until Fup2 is triggered to reset Vfine.…”

“…The effect of data transition probability can be illustrated by substituting (1) into (2). Then, by rearranging, it can be expressed as…”

“…Several related studies [1][2][3][4][5][6][7][8][9][10][11][12][13] have addressed the issues of increasing the oscillation range and enhancing the frequency acquisition range. Unilateral frequency detectors [3][4] are able to correctly detect when the feedback-clock frequency is slower than the received data.…”