8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

“…Weight shifting with compensation was implemented in three stages: (i) weight shifting to increase the number of HRS cells in the cell array; (ii) dot-product computing based on shifted weight data; and (iii) compensation for dot-product results in accordance with the weight shifting value. When storing the weight data of a neural network into the memristor-CIM, each 8-bit weight (W[7:0]) value is shifted by adding a positive bias (B Shift ; e.g., 16) by an on-chip shifting circuit. Note that in typical neural network models, small positive and negative weight values account for the largest proportion of the weights.…”

A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits

“…(1) The sampling structure, consisting of four sampling switches (SW3-SW6) and two sampling capacitors (C0, C1), samples the voltage values of V REFL , V REFH, and V SUM (V REFL = 1/4 VDD, V REFH = 3/4 VDD, V SUM is the input voltage that is quantized); (2) The LSB sensing includes three MOS transistors NO (N1), P0 (P1), P2 (P3), a switch SW1 (SW2), and an inverter, generating the OUT2 (OUT2B) signal for the LSBdetecting circuit; (3) The latch comprises two cascaded inverters formed by N2, P4 and N3, P5 along with two switching MOS transistors (N4, P6), producing SAOUT [1] by comparing the voltages at nodes Q1B and Q1; (4) The LSB-detecting circuit, a 2-to-1 selector, selects between OUT2 and not (OUT2B) based on the value of SAOUT [1] to determine the SAOUT[0] result.…”

“…Concurrently, SW1 and SW2 are turned off, and N0, P0 and N1, P1 formed inverter structures, causing voltage swings at nodes Q2B and Q2 opposite to those at Q1B and Q1, respectively; (3) PH3. This phase accomplishes the output of SAOUT[0] and SAOUT [1]. As Figure 6c illustrates, with SAEN1 = 1, the voltages at Q2 and Q2B are processed through inverters to generate OUT2 and OUT2B, respectively.…”

“…(1) In the first cycle, with VREFH = 1.35 V and VREFL = 0.45 V, the quantization results of MQL-VSA are SAOUT [1]=1 and SAOUT[0] = 1, respectively; (2) In the second cycle, with VREFH = 1.6875 V and VREFL = 1.4625 V, the quantization results are SAOUT [1] = 1 and SAOUT[0] = 1.…”

“…In recent years, AI chips based on computing-in-memory (CIM) architecture are increasingly being integrated into cloud computing, the Internet of Things (IoT), and AI edge devices, demonstrating revolutionary advantages. Among various CIM architectures, those based on resistive random access memory (RRAM) arrays have garnered widespread attention in both academia and industry due to their high integration, low power consumption, low readout latency, and compatibility with traditional CMOS processes [1][2][3]. This makes RRAM-based CIM architectures a potent area for research and application.…”