8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations

Dorojevets, Mikhail; Ayala, Christopher L.; Yoshikawa, Nobuyuki; Tanaka, Masamitsu

doi:10.1109/tasc.2012.2229334

Cited by 27 publications

(7 citation statements)

References 10 publications

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“…Firstly, we note that the number of JJs in RSFQ and RQL logic gates and memory cells is comparable or even larger than in CMOS logic gates and memory. Secondly, superconducting processor architectures that are being developed use algorithms developed for CMOS computers and emulate their architectures, using adders, multipliers, etc., see, e.g., [47], [63]- [67], [71]- [74], [104]. It is reasonable to assume then that a superconducting processor with N junctions operating at f cl will be processing about the same amount of information (perform the same logic and memory functions) as a CMOS-based processor with N transistors clocking at the same frequency.…”

Section: Energy Dissipation and Efficiency Of Scementioning

confidence: 99%

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

Tolpygo¹

2016

Low Temperature Physics

177

115

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Abstract-Superconductor digital electronics using Josephson junctions as ultrafast switches and magnetic-flux encoding of information was proposed over 30 years ago as a sub-terahertz clock frequency alternative to semiconductor electronics based on complementary metal-oxide-semiconductor (CMOS) transistors. Recently, interest in developing superconductor electronics has been renewed due to a search for energy saving solutions in applications related to high-performance computing. The current state of superconductor electronics and fabrication processes are reviewed in order to evaluate whether this electronics is scalable to a very large scale integration (VLSI) required to achieve computation complexities comparable to CMOS processors. A fully planarized process at MIT Lincoln Laboratory, perhaps the most advanced process developed so far for superconductor electronics, is used as an example. The process has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm, and a thin superconducting layer for making compact high-kineticinductance bias inductors. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO 2 interlayer dielectric. The physical limitations imposed on the circuit density by Josephson junctions, circuit inductors, shunt and bias resistors, etc., are discussed. Energy dissipation in superconducting circuits is also reviewed in order to estimate whether this technology, which requires cryogenic refrigeration, can be energy efficient. Fabrication process development required for increasing the density of superconductor digital circuits by a factor of ten and achieving densities above 10 7 Josephson junctions per cm 2 is described.

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Section: Energy Dissipation and Efficiency Of Scementioning

confidence: 99%

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

Tolpygo¹

2016

Low Temperature Physics

177

115

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“…Superconducting circuits: A Josephson junction based processor was proposed as early as 1980 [34]. A number of circuits were demonstrated in RSFQ logic in the 1990s, including DSPs [35], microprocessor components [24,[36][37][38][39], mixed signal devices [40][41][42], floating point units [43,44]. However, due to static power dissipation challenges and high device counts per logic gate, RSFQ circuits faced scalability issues.…”

Section: Related Workmentioning

confidence: 99%

A case for superconducting accelerators

Tannu

Das

Lewis

et al. 2019

Proceedings of the 16th ACM International Conference on Computing Frontiers

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As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower switching energy compared to CMOS. While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: limited device density and lack of area-efficient technology for memory structures, reduced gate fanout compared to CMOS, and new failure modes of Flux-Traps that occurs due to the operating environment.The lack of dense memory technology restricts the use of superconducting technology in the near term to application domains that have high compute intensity but require negligible amount of memory. In this paper, we study the use of superconducting technology to build an accelerator for SHA-256 engines commonly used in Bitcoin mining applications. We show that merely porting existing CMOS-based accelerator to superconducting technology provides 10.6X improvement in energy efficiency. Redesigning the accelerator to suit the unique constraints of superconducting technology (such as low fanout) improves the energy efficiency to 12.2X. We also investigate solutions to make the accelerator tolerant of new fault modes and show how this fault-tolerant design can be leveraged to reduce the operating current, thereby increasing the overall energy-efficiency to 46X compared to CMOS. Our paper also develops a workflow for evaluating area, performance, and power for accelerators built in superconducting technology, and this workflow can help other researchers explore designs using this technology.

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“…In paper [27], Mikhail Dorojevets and Nobuyuki Yoshikawa, proposed, tested and fabricated an ALU design that performs 8 arithmetic and 12 logical operations using wave-pipelining architecture. Finally the authors concluded that the area complexity is more and there were malfunctioning of certain operations.…”

Section: Related Workmentioning

confidence: 99%

An Exhaustive Research Survey on Vedic ALU Design

M¹

2016

IJIRCCE

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ABSTRACT:The digital India is playing an important role nowadays. Indian Vedas and Upanishads are also important and have a great history. That too Vedic mathematics was, is and will be an important basic logic for all mathematical related applications in various fields of science and technology. VLSI is an ever growing field which involves Analog, Digital and Mixed mode Designs. Also in VLSI research, an ALU is a very important system which involves user specifications while designing, for applications like microprocessor, microcontroller, signal processing and various fields. This paper concentrates on the related work on design of Vedic ALU, till date from 46 different IEEE papers and provides some common problem statements and solutions that can be used to design the best ALU, which is not done till date. Importance of reconfigurable feature is also explained in this paper.

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8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations

Cited by 27 publications

References 10 publications

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

Superconductor digital electronics: Scalability and energy efficiency issues (Review Article)

A case for superconducting accelerators

An Exhaustive Research Survey on Vedic ALU Design

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