84 dB 5.2 mA digitally-controlled variable gain amplifier

Nguyen, Hoai‐Nam; Duong, Q. H.; Lee, Sang‐Gug

doi:10.1049/el:20080135

Cited by 17 publications

(37 citation statements)

References 3 publications

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“…From the measurement, the PGA shows that 3 dB bandwidth are 450 MHz. The performance is compared with [3], [4], [5] and [8], which is shown in Table I.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…In order to achieve the desired gain range, gain step and gain error, many VGAs [3,6] have been realized by cascading coarse gain amplifier and fine gain amplifier. As shown in Fig.…”

Section: Proposed Pga Topologymentioning

confidence: 99%

“…1(a), the conventional VGA [2] controlled by analog signals will consume more area and power to achieve dB-linear gain. Digitally controlled VGAs [i.e., programmable gain amplifiers (PGAs)] have also been discussed in some literature [3,4,5], but few of them achieve dB-linear control while producing smaller gain error. Many PGAs [3,6] have adopted two-stage gain control technique which means coarse gain control (CGC) and fine gain control (FGC) to widen the gain control range.…”

Section: Introductionmentioning

confidence: 99%

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A 48-dB precise decibel linear programmable gain amplifier for GNSS receivers

Yin

Zhang

Jin

et al. 2014

IEICE Electron. Express

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A novel circuit architecture for programmable gain amplifier (PGA) is proposed, which simplifies and improves the conventional one and achieves wide precise digital decibel (dB)-linear gain control while obtaining a smaller gain error, smaller chip area and wider bandwidth with low power consumption. In the 0.18-µm CMOS process, the proposed PGA occupies less than 0.09 mm 2 of chip area. From the measurements, the PGA shows a dB-linear gain range of 48 dB (−20 to 28 dB) with a gain error of less than 0.18 dB, a gain step of 0.86 dB, a maximum 1-dB compression point (IP1dB) of 10.4 dBm, and a 3-dB bandwidth of 450 MHz at the maximum gain while consuming only 5.8 mA from a 1.8-V supply.

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“…From the measurement, the PGA shows that 3 dB bandwidth are 450 MHz. The performance is compared with [3], [4], [5] and [8], which is shown in Table I.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…In order to achieve the desired gain range, gain step and gain error, many VGAs [3,6] have been realized by cascading coarse gain amplifier and fine gain amplifier. As shown in Fig.…”

Section: Proposed Pga Topologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 48-dB precise decibel linear programmable gain amplifier for GNSS receivers

Yin

Zhang

Jin

et al. 2014

IEICE Electron. Express

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“…Variable gain amplifiers (VGAs) are key building blocks in many applications to accommodate a large dynamic range of signals, for example, in various wireless communication systems [1][2][3][4][5][6][7]. Beside the large dB-linear control range requirement, high linearity, low noise, and low power consumption are the main challenges in designing VGA.…”

Section: Introductionmentioning

confidence: 99%

“…VGAs are usually implemented in a cascade of many gain stages to satisfy the large dB-linear gain range requirement [1][2][3][4][5][6]. The VGA architecture reported in [7] can provide an 84dB dB-linear gain range, while consuming the smaller power and chip area, compared to those of conventional topology by combining one variable and three fixed gain amplifier stages. According to [7], the gain of variable gain stage is controlled to follow the pseudo-exponential approximation function, e 2x ≈ (1+x)/(1-x), that can provide a dB-linear gain range of 20 dB with less than ±0.25 dB gain error.…”

Section: Introductionmentioning

confidence: 99%

A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier

Han¹,

Nguyen²,

Lee³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a high-linearity lownoise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18-µm CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ±0.33 dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of 0.04 mm 2 and consumes only 1.3 mA from the 1.8 V supply.

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