9.5 A dual-band digital-WiFi 802.11a/b/g/n transmitter SoC with digital I/Q combining and diamond profile mapping for compact die area and improved efficiency in 40nm CMOS

Abstract

Digital transmitters (DTX) have gained interest in the past few years because of their potential to provide compact die area, better efficiency due to the switching nature of the power amplifier core, and scaling with CMOS technology [1][2][3]. Quadrature DTX architecture [1] is favored over polar [3] or outphasing [4] for wideband applications, such as WiFi, because of its ability to scale easily to higher signal bandwidth. Moreover, there is no need for a CORDIC block to convert I/Q signals to amplitude/phase signals [3], which results in large-signal bandwidth expansion, nor the need for very precise alignment [3,4] using fast digital circuits and excessive calibrations. However, the promised potential of quadrature DTX technology fell short of what has been expected because of the excessive parasitics at the TX output as a result of the traditional way of combining the two I and Q paths at the PA output [1]. An I/Q power-cell sharing method by time-division multiplexing between local oscillator (LO) I/Q signals has been proposed for a low-band cellular DPA (800MHz) to address this problem [2]. However, the technique requires 25% LO, which is very difficult to realize for the 5.5GHz WiFi band and is very power hungry. The DTX in Fig. 9.5.1 addresses this issue through a different method of I and Q combining as well as a new digital baseband signal mapping for a compact die area, low parasitics at the PA output, lower loading on LO lines and better overall efficiency.The 10-bit digital I/Q baseband signals are oversampled to half of the carrier frequency (fc/2) for both the 2.4GHz and the 5.5GHz DTX. The selection of fc/2 balances DAC image rejection, timing constraints and digital power consumption in the data path. In fact, the closest DAC images are +/-fc/2 away from the carrier frequency and are attenuated to the IEEE-and FCC-compliant levels by the off-chip diplexer. The signed baseband signals are converted into the sign-magnitude format. There are total of 11 magnitude bits that reach the digital power amplifier (DPA) input, among which there are 6 thermometer bits and 5 binary bits for a good balance between DPA cell mismatch and wiring complexity. The 2.4GHz and 5.5GHz DTX share the same VCO and PLL. The LO generation circuits generate differential 2fc signals by multiplying the VCO frequency by 3/2 in the 2.4GHz DTX and by 3 in the 5.5GHz DTX, and then generate the quadrature (4-phase) 50%-duty-cycle LO fc signals using the divide-by-2 circuits.The input signals of each DPA unary cell in Fig. 9.5.2 include the quadrature LO signals, the I/Q sign bits and the thermo-decoded I/Q enable signals. The LO signals first go through polarity selection set by the sign bits and then are gated by the enable signals through the logic AND function. Each DPA unary cell is controlled by both I and Q enable signals at the same time and I/Q signals are combined at the input of each DPA cell by the logic OR function. Due to the difference between OR function and SUM function, combining the I/Q signals at the input of an...

A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture

“…where R is the average interpolation ratio from t (0) till t h,m . In (18) - (21), it is demonstrated that μ m can yield arbitrary values during the interpolation process. Considering (19) it becomes clear that the major design obstacle for the ASRC is to find an efficient implementation which evaluates the continuous impulse response at arbitrary positions [34], [35].…”

“…11 with 50% LO duty cycle operation is considered. Furthermore, a sharing of the unitary-weighted cells between the I/Q signal components as shown in [21] is assumed. The shared-cell approach is beneficial in order to fully exploit the advantage of the hybrid modulation scheme.…”

“…For the switched-capacitor quadrature RF-DAC with cell sharing between the I/Q components the signal is clipped according to a diamond profile [21]. For this case, signal distortion arises when the number of active RF-DAC cells exceeds the total number of unitary cells N. To avoid additional signal distortion introduced by the clipping, the RF-DAC has to operate in back-off which can be characterized by its maximum output power and the crest factor or PAPR of the applied signal.…”

“…A 50% duty-cycle digital quadrature TX implementation with RF-DPA based on shared, unitary-weighted and dedicated, binary-weighted power cells is shown in [21]. The cell sharing between the I/Q components represents one way to improve the power efficiency.…”

“…However, increased signal distortion is likely to result from the diamond-profile signal clipping which is necessary to avoid simultaneous allocation of cells by the I/Q components. Another cell sharing approach based on timedivison multiplexing is shown in [22], avoiding the diamondprofile clipping of [21] at the drawback of a more complex clocking concept and lower drain efficiency.…”