97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing

Abstract

This paper proposes small array area and memory error tolerant resistive random access memory (ReRAM) computation-in-memory (CiM) with hyperparameter optimization based on bit-error rate (BER) and bit precision of log-encoding simulated annealing (SA). For combinatorial optimization problems, the proposed ReRAM CiM with log-encoding SA reduces the array area by 97.6%, compared with the conventional linear-encoding. To analyze ReRAM device error characteristics, “0” and “1” error injection is applied. The asymmetric ReRAM error improves the acceptable BER by 10 times and the acceptable bit precision to 4 bit. By adjusting the random flips and a cooling parameter, the numbers of flips and iterations decrease by 40% and 33%, respectively. Error injected (EI) iteration is changed to reproduce bit-error due to read disturb. The delay of EI iteration increases the acceptable BER by 25%. Furthermore, in the case of requiring extremely high accuracy, hyperparameter optimization improves the probability of obtaining the optimal answer by 1%.

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

“…23) However, NVM devices have non-ideal properties such as quantization error of memory device conductance, conductance variation, and wearing out by switching. [24][25][26][27][28][29] Figures 9(a) and 9(b) show the measured conductance variation of an ReRAM memory device 30,31) at Set/Reset 10 4 cycles and 10 6 Set/Reset cycles, respectively. ReRAM can switch between HRS and LRS.…”

“…The 0.1%, 1%, and 10% BERs correspond to 1.0 × 10 4 , 4.0 × 10 4 and 2.4 × 10 5 Set/Reset cycles, respectively. 30,31) As described above, bit precision and bit inversion ratio that is directly expressed as BER are key parameters to estimate the impact on inference accuracy under memory device non-ideality.…”

“…On the other hand, ConvLSTM The conductance of 8192 ReRAM cells is measured and inverted cells are counted according to each cycle. 30,31) Layer1 is affected more significantly than ConvLSTM Layer2 since ConvLSTM Layer 1 and Layer2 at 2-bit precision achieve 70% and 80% inference accuracy, respectively. Figure 13 shows bit precision versus the inference accuracy under the condition that the weights of each input and gate in ConvLSTM are quantized independently and the other weights are expressed in 32-bit floating point format.…”

“…11. (Color online) Measured ReRAM Set/Reset cycles versus BER.The conductance of 8192 ReRAM cells is measured and inverted cells are counted according to each cycle 30,31).…”