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The computation of the arctangent of a complex number, i.e. the atan2 function, is frequently needed in hardware systems that could profit from an optimized operator. In the present work we present a novel method to compute the atan2 function and a hardware architecture for its implementation. The method is based on a First Stage that performs a coarse approximation of the atan2 function and a Second Stage that improves the output accuracy by means of a look-up table. We present results for fixedpoint implementations in an FPGA device, all of them guaranteeing last-bit-accuracy, which provide an advantage in latency, speed and use of resources, when compared with well-established fixed-point options.

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“…The schematic diagram of the whole system is shown in Fig. 5, which is analogous to the Kmetz/Maenner method of improving Mitchell's method [9].…”

Section: B Second Stage: Error Reduction Step For the First Stagementioning

confidence: 99%

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number

Torres

Valls

2017

IEEE Trans. VLSI Syst.

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“…As far as dealing with logarithmic numbers with base value 2 (binary logic), there are several procedures followed to ensure correction process for the logarithmic and antilogarithmic conversion circuits. They can summarized as Look Up Table (LUT) based approach [35] [36], improving the accuracy of Mitchell's approach [37] using correction term based, Divided approximation [38]- [41], Operand decomposition [42] [43] and so on. But in the case of TVL, Mitchell's approach cannot be applied, as the approaches do not provide even approximate results for all values in the conversion process.…”

Section: Introductionmentioning

confidence: 99%

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

Valliammal¹,

Palaniswami²

2016

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Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.

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LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS

Arnold

2004

Lecture Notes in Computer Science

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Cited by 19 publications

References 21 publications

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number

A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS

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