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Voltage Regulators Design Through Advanced Mixed-Mode Circuit Simulation

“…6 For the considered values and number of capacitors constituting the bank, k p and k i are updated according to (4). This exit happens when the number of capacitors is reduced from B = 4 to B = 3 when μ 1 is equal to 1.1925 [15], i.e., the T o -periodic 6 SH analyses were performed in tens of seconds on a DELL6600 computer running LINUX; the PAC ones were performed in ≈ 2.5 s. The circuit simulator PAN, developed by the authors, has been used and it is available at the URL: http://brambilla.ws.dei.polimi.it. steady-state solution observed for B = 3 is unstable.…”

“…We compute the μ 1 = 0.2637, μ 2 = 0.0055 ± 0.0099 i main Floquet multipliers (those with significant modulus, the order of the circuit model is well above 3) of the T o -periodic steady-state solution; they are well inside the unit circle in the complex plane and thus the VRM is stable. We compute the R Ao (f ) impedance "seen" by A o through the PAC analysis [6], [14] according to what reported in [7]. R Ao (f ) can be considered as the periodic time-varying transfer function between the current injected by A o and the variation of the V Ao voltage (CPU land).…”

“…In the following, we refer to the conventional shooting (SH) and periodic linear phasor (PAC) analyses providing no details on them since they are widely discussed in the literature (e.g.,[5],[6]). …”