ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) 2014
DOI: 10.1109/esscirc.2014.6942105
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A 0.008-mm<sup>2</sup> area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring

Abstract: An array of temperature sensors based on the temperature-dependent thermal diffusivity of bulk silicon has been realized in a standard 160-nm CMOS process. The sensors achieve an inaccuracy of ±2.4 °C (3σ) from -40 to 125 °C with no trimming and ±0.65 °C (3σ) with a one temperature trim. Each sensor occupies 0.008 mm 2 , and achieves a resolution of 0.21 °C (rms) at 1 kSa/s. This combination of accuracy, speed, and small size makes such sensors well suited for thermal monitoring in microprocessors and other sy… Show more

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Cited by 8 publications
(8 citation statements)
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“…14 (b), the error then reduces to less than 2 m°. A reduction in the phase range can be easily achieved in multi-bit PDΣΔMs or two-step PDΣΔMs [7], thus making such architectures robust to the non-linearity of typical VCO's, which show third-harmonic distortion ranging from -40 to -60 dB.It must be again highlighted that the high tolerance to distortion of the proposed read-out is an inherent property of phase-domain read-outs. Even a large distortion in the amplitude domain at the system input does not significantly affect the phase of the signal, which is the parameter carrying the information to be detected and converted.…”
Section: Non-linearitymentioning
confidence: 98%
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“…14 (b), the error then reduces to less than 2 m°. A reduction in the phase range can be easily achieved in multi-bit PDΣΔMs or two-step PDΣΔMs [7], thus making such architectures robust to the non-linearity of typical VCO's, which show third-harmonic distortion ranging from -40 to -60 dB.It must be again highlighted that the high tolerance to distortion of the proposed read-out is an inherent property of phase-domain read-outs. Even a large distortion in the amplitude domain at the system input does not significantly affect the phase of the signal, which is the parameter carrying the information to be detected and converted.…”
Section: Non-linearitymentioning
confidence: 98%
“…An S bit up/down counter is used to combine demodulation and integration, while an M bit register acts as the quantizer. The quantizer sampling clock (FS) is typically chosen at the same frequency as FDEM [7].…”
Section: Vco-based Pdσδm Architecturementioning
confidence: 99%
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“…For a single-bit modulator, ΦDAC switches between the two phase references, Φ0 and Φ1. FDRIVE and phase DAC outputs can be generated by a digital block, which is driven by an accurate high frequency clock (FSYNC) [12]. However, such PDΣΔMs require large integration capacitors and high-gain amplifiers [12], which in turn occupy significant area.…”
Section: System Level Designmentioning
confidence: 99%
“…However, the reported smart sensor was too large (0.18 mm 2 ) and too slow (1 Sa/s) for thermal monitoring applications. By employing more compact electronics, much smaller smart TD sensors with areas of 8000 μm 2 [12], and even 2800 μm 2 [13], have been reported. However, these sensors were also implemented in a relatively mature 0.16-μm CMOS process.…”
Section: Introductionmentioning
confidence: 99%