A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Muller, Rikky; Gambini, Simone; Rabaey, Jan M.

doi:10.1109/jssc.2011.2163552

Cited by 306 publications

(171 citation statements)

References 22 publications

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“…Many neural signal amplifiers have been developed since 2000 [8][9][10][11], but none of them meets our proposed needs. In former works, some authors implemented simple Operational Transconductance Amplifiers (OTA's) for neural signal amplification based on older technologies (1500 nm to 500 nm).…”

Section: B Neural Signal Amplifiersmentioning

confidence: 99%

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Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier

Gazziro

Braga

Moreira

et al. 2015

2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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Abstract-In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18µm CMOS process technology with all electronics integrated in an area of 0.40mm 2 . The chip has 4 channels, total power consumption of only 144µW, and is impedance matched to silicon carbide biocompatible electrodes. I. INTRODUCTIONAlthough research with Brain Machine Interfaces (BMI) has evolved with great speed in recent years, researchers still do not have reliable BMI systems, which has prevented widespread clinical testing and, ultimately, assisting individuals with neurological and physical disabilities.In order for BMI to effectively make use of the advances in robotic and computer technology, it is vital to find a biological interface that meets the requirements of long-term electrical reliability, low-power operation, and biocompatibility. These requirements are of special importance. First, commonplace systems are based on batteries that eventually discharge and must be replaced after short periods of time, resulting in additional maintenance requirements; Second, many systems rely on materials that may not have reliable biocompatibility, and can possibly erode with time, demanding costly and high-risk replacement procedures [1][2]. In this paper, our contribution focuses on addressing these two issues.This project describes the development of a wireless BMI system -see Figure 1, with constraints of very low-power consumption and biocompatibility. Our solution relies on two features: (1) we use a chip designed to operate with a power consumption that is small enough for it to be powered by radio frequency antennas, dispensing with the need for batteries; (2) we use a probe manufactured from silicon carbide (SiC), a material that demonstrated excellent neural compatibility with murine mouse brain tissue in vivo [13]. This paper presents the first version of the Cortex chip, which is a 4-channel amplifier that magnifies neural signals to levels high enough for them to be processed by a computer. Fig. 1. Conceptual diagram of the proposed BMI system, which integrates the Cortex chip, described in detail in this paper, with cubic silicon carbide electrodes (3C-SiC) and an RFID wireless interface. II. CONCEPTS AND RELATED WORKS A. Gliosis and Neural ImplantsThe introduction of neural interfaces inside the central nervous system (CNS) inevitably damages the delicate tissue which leads to the neural inflammitory response, gliosis [1][2][3][4][5]. Gliosis is a reactive cellular process concerning physiological changes in glial cell...

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Section: B Neural Signal Amplifiersmentioning

confidence: 99%

“…Some authors [11] completely avoid the use of on-chip (and even off-chip) capacitors, to minimize power consumption. This design decision forces them to use DC coupling (instead of AC coupling) at the amplifier input, forcing them to deal with DC component elimination a posteriori.…”

Section: B Neural Signal Amplifiersmentioning

confidence: 99%

Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier

Gazziro

Braga

Moreira

et al. 2015

2015 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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“…The main disadvantage of these approaches is that the cut-off frequency of each recording channel is prone to different variations [4]. A digitally assisted servo loop can be used to overcome this issue by controlling the corner frequency in the digital domain [4], [13], [27]- [29]. However, the stability of a digitally assisted servo loop is impacted by the latency of the digital filter.…”

Section: Introductionmentioning

confidence: 99%

“…Another drawback of this solution is that a charge-redistribution DAC is directly driven by the fluctuating electrode-tissue impedance, which can introduce distortion in the readout due to finite input impedance. To circumvent this issue, a DC-coupled neural recording interface with a current-steering DAC was used in [4] and [27], but with a limited peak input (± 50 mV). Although the aforementioned techniques are effective for rejecting the electrode offset in traditional neural recording interfaces, a different approach is needed for brain stimulation systems.…”

Section: Introductionmentioning

confidence: 99%

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Ivanisevic

Rodriguez

Rusu

2018

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 µm CMOS triple-well process and has a total power consumption of 54 µW. Measurement results, across ten packaged samples, show approximately 14-ENOB over a 300 Hz bandwidth with an input referred noise of 5.23 µVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

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“…Therefore, one needs to propose solutions to both effectively utilize the available power and area budgets, and not to deteriorate other important parameters. There are many prominent examples of systems that present different approaches for recording channels architecture [3,6,[13][14][15][16]. In this paper, the design of the whole recording path is presented with the emphasis on the methods allowing for minimization of both power and area with no negative influence on other system parameters.…”

mentioning

confidence: 99%

Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments

Kmon¹

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. This paper presents techniques introduced to minimize both power and silicon area of the multichannel integrated recording circuits dedicated to biomedical experiments. The proposed methods were employed in multichannel integrated circuit fabricated in CMOS 180nm process and were validated with the use of a wide range of measurements. The results show that both a single recording channel and correction blocks occupy about 0.061 mm 2 of the area and consume only 8.5 µW of power. The input referred noise is equal to 4.6 µV RMS . With the use of additional digital circuitry, each of the recording channels may be independently configured. The lower cut-off frequency may be set within the range of 0.1 Hz-700 Hz, while the upper cut-off frequency, depending on the recording mode chosen, can be set either to 3 kHz/13 kHz or may be tuned in the 2 Hz-400 Hz range. The described methods were introduced in the 64-channel integrated circuit. The key aspect of the proposed design is the fact that proposed techniques do not limit functionality of the system and do not deteriorate its overall parameters. minimization of power consumption affects the IRN whilst recording channels area minimization may limit the functionality of the system, have adverse effect on the IRN or deteriorate uniformity of its main parameters. Therefore, one needs to propose solutions to both effectively utilize the available power and area budgets, and not to deteriorate other important parameters. There are many prominent examples of systems that present different approaches for recording channels architecture [3,6,[13][14][15][16]. In this paper, the design of the whole recording path is presented with the emphasis on the methods allowing for minimization of both power and area with no negative influence on other system parameters.The paper is organized as follows. In Section 2, the design of a recording channel is presented with a special attention paid on its power consumption and area occupation. Section 3 provides information regarding analog multiplexer where techniques for the area and power minimization are also presented. Section 4 looks at the measurement results of designed multichannel recording circuits, while Section 5 provides conclusions.

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A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Cited by 306 publications

References 22 publications

Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier

Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments

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A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Cited by 306 publications

References 22 publications

Transmission of wireless neural signals through a 0.18&#x00B5;m CMOS low-power amplifier

Transmission of wireless neural signals through a 0.18&#x00B5;m CMOS low-power amplifier

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments

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Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier

Transmission of wireless neural signals through a 0.18µm CMOS low-power amplifier