A 0.0175mm<sup>2</sup>600µW 32kHz input 307MHz output PLL with 190ps&lt;inf&gt;rms&lt;/inf&gt; jitter in 28nm FD-SOI

Lahiri, Abhirup; Gupta, Nitin

doi:10.1109/esscirc.2016.7598311

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…10(a) shows two examples, which are used in Refs. [42,43]. The main design challenge of these capacitance multipliers is that the op amp requires low noise and large output voltage range simultaneously.…”

Section: Area Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

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Section: Area Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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“…As aforementioned, its BW loop can be limited to be less than 3 kHz with 32-kHz reference. This narrow bandwidth will lead the DCO phase noise to deteriorate the output jitter performance [15]. The type I PLL [11], [16] or the injection lock PLL [17], [18], which can realize 40% or 50% f REF BW loop in theory, face the same problem of limited BW loop .…”

Section: Introductionmentioning

confidence: 99%

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

Qiu

Sun

Liu

et al. 2021

IEEE J. Solid-State Circuits

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In this article, a mixed-signal, 32-kHz referencebased 2.4-GHz fractional-N over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional 1× sampling PLL, which only uses zero-crossing timing information of the reference signal, the proposed OSPLL fully utilizes both the voltage and timing domain information of the reference signal and realizes oversampling ratio (OSR) times phase detection (PD) in one reference cycle. The proposed OSPLL employs the digitalto-analog converter (DAC) to construct the reference-like feedback signal in the voltage domain and utilizes the digital-to-time converter (DTC) to improve PD resolution in the time domain. The adaptive lookup table (LuT)-based calibration is proposed to generate the correct information for DAC and DTC control. A clocked passive comparator works as a bang-bang phase detector (BBPD) for the PLL control and LuTs' construction. The co-design of low-noise analog circuits and digital calibrations enables good jitter and spur performance. The proposed OSPLL is fabricated in 65-nm CMOS technology, with the core area of 0.58 mm 2 , and the power consumption is 4.97 mW with a 1-V power supply. It achieves 5.79-ps root-mean-square (rms) jitter in fractional-N modes with the loop-bandwidth (BW loop ) of 200 kHz, corresponding to the figures of merit (FoMs) of −217.8 dB. The measured fractional spur is less than −36 dBc, and the reference spur is −78 dBc, respectively.

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FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs

Cathelin

2017

Hybrid ADCs, Smart Sensors for the IoT, and Sub-1v &Amp; Advanced Node Analog Circuit Design

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A 0.0175mm²600µW 32kHz input 307MHz output PLL with 190ps<inf>rms</inf> jitter in 28nm FD-SOI

Cited by 3 publications

References 5 publications

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops: An overview

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs

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A 0.0175mm2600µW 32kHz input 307MHz output PLL with 190ps<inf>rms</inf> jitter in 28nm FD-SOI

Cited by 3 publications

References 5 publications

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops: An overview

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth

FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs

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A 0.0175mm²600µW 32kHz input 307MHz output PLL with 190ps<inf>rms</inf> jitter in 28nm FD-SOI