A 0.0375mm<sup>2</sup> 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

Lee, Calvin Yoji; Moon, Un-Ku

doi:10.1109/isscc42614.2022.9731606

Cited by 9 publications

(5 citation statements)

References 1 publication

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“…When compared to the previous CT zoom ADC [3], this design achieves higher energy efficiency (FoMSNDR) over a somewhat wider bandwidth (24 kHz versus 20 kHz), demonstrating the effectiveness of the techniques used in this work. The ADCs in [1,9] have better FoM but are DT and require high-power input buffers to drive their switchedcapacitor front ends, resulting in overall higher system power. The ADCs in [6,7,8] have higher energy efficiency but are realized in more advanced technologies resulting in significantly lower digital power and area, especially for clock generation and the DWA logic.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Mehrotra

Eland

Karmakar

et al. 2022

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a continuous-time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip occupies 0.36 mm 2 , achieves 107.2 dB SNR, 106.6 dB SNDR, and 107.3 dB dynamic range in a 24 kHz bandwidth while consuming 590 µW from a 1.8 V supply. This translates into a Schreier figure-ofmerit (FoMS) of 183.4 dB and a FoMSNDR of 182.7 dB. Keywords-A/D conversion, audio analog to digital converter (ADC), continuous-time delta-sigma ADC, dynamic zoom ADC, low-power circuits, noise-shaping SAR ADC, high linearity operational transconductance amplifier (OTA)

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Section: Measurement Resultsmentioning

confidence: 99%

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Mehrotra

Eland

Karmakar

et al. 2022

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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“…Lee and Moon [117] proposed the single-ended ring amplifier with the pseudo-pseudo-differential (PPD) architecture in the first integrator. The pole of the first stage is placed out-of-band so that the stability of the second and third stages is not compromised.…”

Section: ) Active Integratorsmentioning

confidence: 99%

“…2, the work competes with the much more recent work from [126] but achieves an FoM S of only 158 dB, about 25 dB worse than the leading SOTA today. Three more energy-efficient audio ADCs are mentioned here, first, the work of Lee and Moon [117], where a DT single-loop ADC is implemented using ring-amplifier-based integrators in a mature 180-nm CMOS process. Lo et al [129] proposed a CT ADC, which offers easier drivability and an implicit anti-aliasing filter, in contrast to [117].…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

“…Three more energy-efficient audio ADCs are mentioned here, first, the work of Lee and Moon [117], where a DT single-loop ADC is implemented using ring-amplifier-based integrators in a mature 180-nm CMOS process. Lo et al [129] proposed a CT ADC, which offers easier drivability and an implicit anti-aliasing filter, in contrast to [117]. It uses a tri-level DAC like [128] but is based on a currentsteering DAC.…”

Section: ) Techniques For Narrowband Adcsmentioning

confidence: 99%

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Design Techniques for Energy-Efficient Analog-to-Digital Converters

Jang,

Tang,

Lim

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the past 40 years, with the best reported ADC efficiency improving by nearly six orders of magnitude over the same period. The best figure-of-merit (FoM) is achieved with a limited class of ADC in terms of resolution and speed, but the coverage of the best FoM ADC has been expended. Many ADCs with the record FoM open up new applications and often incorporate multiple combinations of architectural and circuit innovations. It would be very interesting to follow a path of relentless optimization that could be useful to further expand the operating bandwidth of energy-efficient ADCs. To help along this path, this review article discusses the design techniques that focus on optimizing energy efficiency, involving successive approximation, pipelining, noise-shaping, and continuous-time operation.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT), delta-sigma modulation, energy efficient, low power, noise-shaping (NS), pipelining, successive approximation.

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“…The capacitive digital-to-analog converter (C-DAC) is a popular type of DAC, which produces output voltage through charge redistribution between capacitors. C-DACs are especially widely used as auxiliary DACs in analog-to-digital converters (ADCs) such as delta-sigma ADCs, SAR ADCs, or pipelined ADCs, which require DACs to produce feedback signal which should be compared with the input signal [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. An important characteristic of a C-DAC is the dynamic power consumption associated with the switching of the C-DAC.…”

Section: Introductionmentioning

confidence: 99%

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

et al. 2023

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Capacitive DACs (C-DACs) are widely used as stand-alone DACs or in an ADC as auxiliary DACs. An important performance metric of a C-DAC is its energy consumption and the linearity between the digital input and the analog output. In multi-bit C-DACs, the mismatch between the capacitors can degrade linearity, which can be important in high-resolution applications. In this work, we analyze the power consumption and linearity performance of a class of C-DACs called split-array C-DACs. We show that the simple element rotation technique, which is widely used to suppress the mismatch error of DACs, cannot be used with the power-efficient three-level switching scheme to effectively suppress the mismatch error. Then, we propose a switching scheme which can be used with the power efficient three-level switching and can suppress the in-band mismatch error effectively.

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A 0.0375mm² 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

Cited by 9 publications

References 1 publication

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

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A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS

Cited by 9 publications

References 1 publication

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

Design Techniques for Energy-Efficient Analog-to-Digital Converters

Mismatch-Shaping Switching Scheme for Split-Array Capacitive DACs

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A 0.0375mm² 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS