A 0.1–1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

Abstract

A 0.1–1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3–6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal–oxide–metal (MOM) capacitor, occupies 0.05 mm2 silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is −102 dBc/Hz @ 1 MHz offset frequency.