A 0.1–13 GHz Wide Range Multi-Modulus Divider with Adaptive Sensitivity for Broad Band Operation

Kreisig, Martin; Buhr, Simon; El-Shennawy, Mohammed; Ellinger, Frank

doi:10.1109/mwscas.2018.8624050

Cited by 2 publications

(3 citation statements)

References 9 publications

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“…In order to strengthen the applicability of the clock generator by increasing the loop divider ratio, methods such as compressing the reference clock frequency range and expanding the divider ratio of MMD can be implemented. Prior research generally confirms that the division ratio extension is invariably achieved by improving two dimensions of integer or fractional-N division accuracy [11,12]. While the MMD is composed of the prescalers and the counters expand the logic control bit width of the counter, the consumption of hardware cannot be ignored.…”

Section: Introductionmentioning

confidence: 93%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

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Section: Introductionmentioning

confidence: 93%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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“…Therefore, the area of the whole system and the power consume of the whole system can be reduced [18]. A 2/3 divider-chain is a common structure of MMD [19][20][21][22][23][24][25]. The division ratio of such MMD ranges from 2 n to 2 n+1 − 1, where n is the amount of the 2/3 divider cell.…”

Section: Analysis Of Dividers In Pllmentioning

confidence: 99%

“…The structure of MMD contains three parts: dual-modules prescaler, program counter (counter P) and swallow counter (counter S). A 2/3 divider-chain is a common structure of MMD [19][20][21][22][23][24][25]. The division ratio of such MMD ranges from 2 n to 1 2 1 n   , where n is the amount of the 2/3 divider cell.…”

Section: Circuit Design Of MMDmentioning

confidence: 99%

A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

et al. 2020

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High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

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A 0.1–13 GHz Wide Range Multi-Modulus Divider with Adaptive Sensitivity for Broad Band Operation

Cited by 2 publications

References 9 publications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

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