As scaling reduces the breakdown voltage of CMOS devices and as system integration trends demand the further elimination of offchip components, there arises a great need to improve the linearity of RF receivers. Of particular interest is the direct-conversion architecture, which is currently the workhorse of the mobile telecommunications industry. Although much work has been recently reported in improving the IIP2 of these receivers, the IIP3 requirements still necessitate the use of an inter-stage SAW filter in many applications.In order to remove the SAW filter and to reduce the linearity requirements of the receiver circuitry, in this paper, an alternate path (AP) in parallel with the main path (MP) is introduced (Fig. 10.3.1). The AP generates IM3 products in the analog domain and downconverts them to baseband (BB) using the same LO signal as the MP. The IM3 products are then digitized and used as inputs to an equalizer that cancels the baseband IM3 products in the MP. This idea has recently been posited in a system-level study [1]; however, the challenges of implementing this system with an integrated RF front-end have not yet been addressed. This solution has the advantages of being both power-efficient and robust. Since the AP must only pass IM3 products, the dynamic ranges of its constituent blocks can be over 10dB less than those of the MP, allowing for significant power savings in its overall design. As problematic blocker conditions occur less than 10% of the time, the time-averaged power dissipation of the AP is further reduced from its nominal value by powering it on only when needed. The adaptive nature of the equalization guarantees robustness in the presence of changes in temperature, LO frequency, and blocker characteristics.The receiver architecture proposed in this paper is shown in Fig. 10.3.2. In order to provide a quantitative design objective, the UMTS standard is targeted. The single-ended-to-differential conversion previously handled by an inter-stage SAW filter is now performed by a balun. The balun is followed by high-IIP2 MP mixers [2] driven by Cherry-Hooper LO buffers. The MP BB filter is an active-RC 3 rd -order Chebyshev architecture that drives an 8b pipelined ADC with f s =50MHz. The AP is a scaled-down version of the MP, with the primary difference being the inclusion of an IM3 generator. For area efficiency, the AP mixer dispenses with the IM2 tuning inductor used in the MP while resistively loaded differential pairs serve as LO buffers. The AP 1 st -order BB filter drives an 8b pipelined ADC with f s =16.66MHz.In a proper design, the IM3 generator requires a dynamic range of 10dB above the desired IM3 cancellation ratio. Unlike other approaches [3] that use the 3 rd -order Taylor series term of the MOSFET, this design, shown in Fig. 10.3.3, exploits the stronger 2 nd -order term by using a conventional squaring circuit and by finishing the cubing with a Gilbert multiplier. Two Gilbert multipliers in series also accomplish a cubing, but generate a higher IM5 product since th...