A 0.18-&amp;#x00B5;m CMOS, &amp;#x2212;92-dB THD, 105-dB&lt;inf&gt;A&lt;/inf&gt; DR, third-order audio class-D amplifier

Cartasegna, D.; Malcovati, P.; Crespi, L.; Basçhirotto, A.

doi:10.1109/esscirc.2013.6649099

Cited by 2 publications

(4 citation statements)

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“…It remains unclear why the f sw regulated case has higher distortion than the fixed frequency cases. For applications that require lower distortion, a higher-order feedback loop can be used, either for hysteretic feedback [25] or fixed carrier [26], [27] topologies.…”

Section: Measurement Resultsmentioning

confidence: 99%

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

Zee

Nauta

2015

IEEE J. Solid-State Circuits

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This paper describes the power dissipation analysis and the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. Implemented in a 0.14µm SOI BCD process, the amplifier achieves 93% efficiency at 45W output power, >80% power efficiency down to 4.5W output power and >49% efficiency down to 0.45W output power.

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Section: Measurement Resultsmentioning

confidence: 99%

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

Zee

Nauta

2015

IEEE J. Solid-State Circuits

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show abstract

“…A varying common-mode level of Vtune level might be one of the contributing factors. For applications that require lower distortion, a higher-order feedback loop can be used, either for hysteretic feedback [49] or fixed carrier [50], [51] topologies.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Class-D power stage non-idealities introduce distortion to the amplifier's output signal [47], [48]. Feedback loop gain can suppress these error and various high-order feedback loops with sufficient loop gain are implemented for this reason [49]- [51]. Yet it has been shown that higher-order loop filters does not necessarily mean better linearity performance due to the extra error introduced by the PWM-based feedback loop itself [52]- [54].…”

Section: Linearitymentioning

confidence: 99%

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High-voltage class-D power amplifiers

Ma¹

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Nowadays transducers are ubiquitous as interfaces between the increasingly digital world and the real physical world. The same holds for the power amplifiers driving them. This thesis focuses on the design and optimization of high-voltage class-D amplifiers, which are used for driving capacitive piezoelectric actuator loads in active vibration/noise control applications.The main objective is to further enhance class-D power efficiency compared to existing class-D designs.To gain insight in class D power efficiency, a detailed analysis of high-voltage class-D dissipation sources is performed and a dissipation model including all the major dissipation sources is developed. The analysis shows that switching loss is a potential dominating dissipation source in high-voltage applications, while its contribution can be minimized by fast switching to eliminate V-I overlap losses. Moreover, it is shown that when varying the class-D switching frequency, a minimum total dissipation exists, with the optimal switching frequency depending on the output power. Furthermore, idle loss reduction by increasing the switching frequency and inserting a dead time to the power stage is backed by the analysis.Following the analysis, a fast-switching power stage is designed to aim for switching loss minimization. This output stage design features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transitions and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip. In addition, gate driver sizing procedures for the class-D output stage are discussed, showing that the variable gate driving strength can greatly improve efficiency when on-chip supply bounce is the limiting factor.Also based on the dissipation analysis, this thesis describes the design of an efficiencyimproved high-voltage class-D power amplifier. The amplifier adaptively regulates its

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A 0.18-µm CMOS, −92-dB THD, 105-dB<inf>A</inf> DR, third-order audio class-D amplifier

Cited by 2 publications

References 5 publications

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range

High-voltage class-D power amplifiers

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