A 0.18 μm 4 Mbit toggling MRAM

Durlam, M.; Addie, D.; Åkerman, Johan; Butcher, B.; Brown, P.; Chan, J.; DeHerrera, M.; Engel, Brad N.; Feil, B.; Grynkewich, G.; Janesky, J.; Johnson, Mark; Kyler, K.; Molla, J.; Martin, John F.; Nagel, K.; Nahas, Joseph; Ren, Jinjun; Rizzo, N.D.; Rodrı́guez, T.; Savtchenko, L.; Salter, J.; Slaughter, J. M.; Smith, K.; Sun, J. J.; Lien, M.; Papworth, K.; Shah, P.; Qin, Wentao; Williams, R.; Wise, L.; Tehrani, S.

doi:10.1109/icicdt.2004.1309899

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…Solid state magnetic memories started to be developed following the discovery of the Giant Magneto-Resistive Effect in thin films in 1988. A 4 Mb device was presented at IEDM in 2003 [17]. The basic mechanism device is a tunnel diode with a thin dielectric sandwiched between two magnetic layers.…”

Section: Magnetic Memoriesmentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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a b s t r a c tMemory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.

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Section: Magnetic Memoriesmentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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“…An innovative solution was published in 2003 [40]. As shown in Figure 17(a), a special MTJ device called Savtchenko device was designed.…”

Section: Magnetic Memory (Mram)mentioning

confidence: 99%

State-of-the-art flash memory devices and post-flash emerging memories

Lue

Chen

2011

Sci. China Inf. Sci.

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Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined. State-of-the-art floating gate flash memoryFlash memories have become ubiquitous in consumer electronics, mobile devices and PC and enterprise applications [1]. The basic operation principle of flash memory device is to store electrons in a floating gate (FG) or a charge-trapping layer (such as SONOS) and accordingly the Vth of the MOSFET devices is changed and identified as the stored logic state. The older EEPROM (electrically erasable and programmable read only memory) uses two transistors to provide RAM-like random access and bit alterable features. Flash memory gives up the bit alterable feature and adopts a block erase (flash) to achieve a 1-transistor (1T) cell that allows much higher density. Over the years, the array architecture has converged into NOR and NAND types (Figure 1) for different applications.NOR Flash device uses channel hot electron (CHE) injection for programming and has retained fast random access capability suitable for code storage applications. The random access feature requires a

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“…In the early days, MRAM used the FIMS switching technique [19], which switches the magnetization using a magnetic field induced by the conducting lines adjacent to the MTJ, as shown in Figure 1(a). If the current flow is sufficient to produce a critical magnetic field, the direction of magnetization in the ferromagnetic layer switches to the opposite direction.…”

Section: Development History Of Switching Technology Switching Technmentioning

confidence: 99%

A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation

Lim

Lee

Shin

2016

Active and Passive Electronic Components

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Spin-transfer torque-based magnetoresistive random access memory (STT-MRAM) is a promising candidate for universal memory that may replace traditional memory forms. It is expected to provide high-speed operation, scalability, low-power dissipation, and high endurance. MRAM switching technology has evolved from the field-induced magnetic switching (FIMS) technique to the spin-transfer torque (STT) switching technique. Additionally, material technology that induces perpendicular magnetic anisotropy (PMA) facilitates low-power operation through the reduction of the switching current density. In this paper, the modeling of magnetic tunnel junctions (MTJs) is reviewed. Modeling methods and models of MTJ characteristics are classified into two groups, macromodels and behavioral models, and the most important characteristics of MTJs, the voltage-dependent MTJ resistance and the switching behavior, are compared. To represent the voltage dependency of MTJ resistance, some models are based on physical mechanisms, such as Landau-Lifshitz-Gilbert (LLG) equation or voltage-dependent conductance. Some behavioral models are constructed by adding fitting parameters or introducing new physical parameters to represent the complex switching behavior of an MTJ over a wide range of input current conditions. Other models that are not based on physical mechanisms are implemented by simply fitting to experimental data.

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A 0.18 μm 4 Mbit toggling MRAM

Cited by 5 publications

References 3 publications

Emerging memories

Emerging memories

State-of-the-art flash memory devices and post-flash emerging memories

A Survey on the Modeling of Magnetic Tunnel Junctions for Circuit Simulation

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