A 0.2–2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer

Design Techniques for High-Speed I/Os: Challenges and Opportunities

“…Eye-opening can be captured using an Eye-Opening Monitor (EOM) [73][74][75][76][77][78][79][80][81]. Jitter-based eye-opening monitors that minimize timing jitter at the edges of data eyes also emerged [82]. Dual-mode adaptive DFE consisting of a data-DFE to maximize vertical opening and a jitter-DFE to minimize timing jitter outperforms EOM-based DFE [49].…”

Minimum jitter adaptive decision feedback equalizer for 4PAM serial links

“…Although 2-dimensional EOMs do have a constraint on data jitter, it is lower-bound by the vertical eye-opening at the center of the data eye. In [4], jitter information at the edges of data eyes is obtained by employing a set of temporally spaced samplers that sample the transition edge of the eyes at uniformly incremented time instants. The dualmode adaptive DFE proposed in [5] consists of a data DFE for maximizing the vertical opening of data eyes and a jitter DFE for minimizing the jitter at the edges of data eyes.…”

On-chip data communication : analysis, optimization and circuit design

“…The first flavor is continuous-time equalization, with (HF) boosting circuits that compensate for the attenuation of the channel, also called 'linear equalization' [117,123,[125][126][127][128][129][130][131][132][133]. This flavor has the longest history and is still being used in many contemporary transceivers, but its popularity seems to diminish because of another equalization form, the so called 'Decision-feedback equalization' (DFE) [98, 111-116, 119, 134-138].…”

“…A similar method is to compare the slope before and after the detector [130]. The adaptation can also be done digitally, by for example analyzing the histogram of the data-edges with an oversampled receiver [132].…”

“…But even when the clock is already known in the receiver, or in sourcesynchronous links where a (possibly low frequent) reference clock is send along the data channels, CDR's can still be found to multiply the frequency of the clock and get phase alignment [127,132,145]. Once the frequency of the recovered clock is known, control of the clock generator phase is either done continuously or through the selection of one clockphase from a finite set of possible phases (creating a sort of 'digital' CDR [132]). …”