A 0.25 mu m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs

0.6 V suppy voltage 0.25 μm E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

“…We obtained fan-in delay of 2 ps, fan-out delay of 10 ps, and wiring delay of 67 ps/mm, and hence standard propagation delay with FI-F0=3 and L=l mm is estimated to be 109 ps. All of these values were nearly equal to the simulated values [2]. A!…”

“…The process flow of fabricating individual W E T S is basically the same as that described in reference [2]. The improved technology, however, makes it possible to perform low damage AlGaAs/GaAs selective dry etching for precise threshold voltage control both of E-and D-HJFETs, WSDi/Pt/Au multilayer gate metallization to achieve both reliable and lower resistance gate electrodes leading to higher fmax, and low stress S O N passivation to minimize the effect of stress-induced piezoelectric charge.…”

“…Since compound semiconductor devices have inherently high electron mobility, a very low drain current saturation voltage can be easily realized if their parasitic resistances could be markedly reduced. The previously reported 0.25 pm inner sidewall-assisted super self-aligned gate heterojunction(HJ) FETs [2] are very attractive because they make it possible to attain low parasitic resistances without degrading the excellent intrinsic characteristic. Here, we extend the technology used to fabricate them to include co-integration of enhancement(E) and depletion(D) mode HJFETs, and examine its application feasibility for low supply voltage LSIs by fabricating several kinds of loaded and unloaded ring oscillators and a selector switch on the basis of direct coupled FET logic (DCFL) circuits.…”