A 0.25-V calibration-less inverter-based OTA for low-frequency G-C applications

Braga, Rodrigo Aparecido da Silva; Ferreira, Luís H. C.; Coletta, Gustavo D.; Dutra, Odilon O.

doi:10.1016/j.mejo.2018.11.008

Cited by 30 publications

(19 citation statements)

References 17 publications

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“…The simulations show 6.3 and 5.4 mV input offset voltage for 3σ mismatch variation for OTA-A and OTA-B, respectively. Such effect could be compensated by an additional calibration network [25] or by increasing the transistor arrays' sizes [20]. Table 2 summarizes the corner simulation results.…”

Section: Unity-gain Buffer Analysismentioning

confidence: 99%

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Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

2020

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This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

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Section: Unity-gain Buffer Analysismentioning

confidence: 99%

“…In this framework, the composite transistors [19], such as rectangular arrays [20] and trapezoidal arrays [21], can be used to increase the voltage gain of inverter-based OTAs at the cost of area.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

2020

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“…The ULV DB-OTA operation can be severely impaired by process variations and mismatch in the trip points V T [32] of the first inverters of the DM amplifier, which result in an input offset voltage [15]:…”

Section: Process Variations and Mismatchmentioning

confidence: 99%

“…∆t D is the difference in the propagation delays of the two branches of the OTA, I OUT is the output stage current (assumed to be fixed for the sake of simplicity), I D0 N(P) is the zero-v GS drain current of nMOS (pMOS) in weak inversion and it is process parameter dependent, n N(P) is the subthreshold slope factor of the nMOS (pMOS) device. All the other symbols have their usual meaning [32]. For minimum-size devices, the offset predicted by Equation (3) can be easily large enough to saturate the DB-OTA, thus fully impairing the DB-OTA operation, and needs to be compensated.…”

Section: Process Variations and Mismatchmentioning

confidence: 99%

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

et al. 2020

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The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

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“…Em (R. A. Braga, Ferreira, Colletta, & Dutra, 2017;R. A. Braga, Ferreira, Colletta, & Dutra, 2019) é apresentado uma implementação para o amplificador operacional de transcondutância fully diferencial baseado em inversores CMOS construídos com transistores MOS matriciais haloimplantados em um processo CMOS de 130 nm.…”

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Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm

Silva

Braga

Karolak

et al. 2020

RSD

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In manufacturing processes of integrated differential amplifiers, an inherent characteristic is that the fabricated nMOS and pMOS transistors have physical differences in relation to the projected values, an effect known as mismatch. In this work, the manufacturing process variations in operational transconductance amplifiers (OTA) are evaluated. Two OTA based on CMOS inverters are designed using both low threshold and standard threshold uniformly doped transistors using quantitative experimental research.

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A 0.25-V calibration-less inverter-based OTA for low-frequency G-C applications

Cited by 30 publications

References 17 publications

Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm

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